ADF4377 datasheet(10/79 Pages) AD

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Data Sheet

ADF4377

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 10 of 79

Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

1, 2, 4, 10, 12,

14, 16, 18, 19,

21, 23, 25, 26,

41, 48

GND

Negative Power Supply (Ground). These pins must be tied directly to the ground pad.

V3_NDIV

3.15 V to 3.45 V Positive Power Supply Pin for the PLL Feedback Divider Circuitry. Short this pin to the other pins in 3.3 V Power Supply

Group 1.

V3_VCO

3.15 V to 3.45 V Positive Power Supply Pin for the 3.3 V Portion of the VCO Circuitry. Short this pin to the other pins in 3.3 V Power

Supply Group 2.

DCLBIAS

Do not connect to this pin.

VTUNE

VCO Tuning Input. This frequency control pin is normally connected to the external loop filter.

V5_CAL

4.75 V to 5.25 V Positive Power Supply Pin for VCO Calibration Circuitry. This pin can be shorted to the V5_VCO supply plane.

V5_VCO

4.75 V to 5.25 V Positive Power Supply Pin for the 5 V Portion of the VCO Circuitry.

V3_CLKDIV

3.15 V to 3.45 V Positive Power Supply Pin for the Output Divider Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 2.

V3_CLK2

3.15 V to 3.45 V Positive Power Supply Pin for the Clock 2 Buffer Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 2.

15, 17

CLK2N, CLK2P

Clock 2 Output Signal. The VCO output divider is buffered and presented differentially on these pins. The outputs have 50 Ω (typical)

output resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the

outputs. The output amplitude is programmable via the serial port.

20, 22

CLK1N, CLK1P

Clock 1 Output Signal. The VCO output divider is buffered and presented differentially on these pins. The outputs have 50 Ω (typical)

output resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the

outputs. The output amplitude is programmable via the serial port.

V3_CLK1

3.15 V to 3.45 V Positive Power Supply Pin for the Clock 1 Buffer Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 2.

LKDET

PLL Lock Detect. This output presents the lock status of the PLL. PLL is locked when the LKDET pin is a logic high.

ENCLK2

Enable Clock 2 Output Buffer. 1.8 V and 3.3 V compatible CMOS input. When ENCLK1 = high, the CLK2P and CLK2N output buffer is

active. When ENCLK2 = low, the CLK2P and CLK2N output buffer is powered down.

ENCLK1

Enable Clock 1 Output Buffer. 1.8 V and 3.3 V compatible CMOS input. When ENCLK1 = high, the CLK1P and CLK1N output buffer is

active. When ENCLK1 = low, the CLK1P and CLK1N output buffer is powered down.

V3_LS

3.15 V to 3.45 V Positive Power Supply Pin for the Internal Level Shift Circuitry. Short this pin to the other pins in 3.3 V Power Supply

Group 1.

Chip Enable. 3.3 V CMOS input. Does not support 1.8 V CMOS levels. This CMOS input enables the device when driven high. A logic low

disables the device, putting the device in a full power-down state, causing the registers to reset. Conversely, the PD_ALL bit powers down

the device, but does not reset the registers.

CSB

Serial Port Chip Select. 1.8 V and 3.3 V compatible CMOS input. This CMOS input initiates a serial port communication burst when driven

low, ending the burst when driven back high.

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