ADF4377 datasheet(57/79 Pages) AD

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Data Sheet

ADF4377

analog.com

Rev. 0 | 57 of 79

Table 62. Bit Descriptions for REG0017

Bits

Bit Name

Description

Reset

Access

0: not inverted.

1: inverted.

[6:0]

N_DEL

Feedback Delay. Decreases reference input to clock output propagation delay. Double buffering option.

0x0

R/W

Address: 0x18, Reset: 0x00, Name: REG0018

Figure 126.

Table 63. Bit Descriptions for REG0018

Bits

Bit Name

Description

Reset

Access

CMOS_OV

Logic High Voltage for MUXOUT, LKDET, SDO, SDIO.

0x0

R/W

0: 1.8 V logic.

1: 3.3 V logic.

[6:0]

R_DEL

Reference Delay. Increases reference input to clock output propagation delay. Double buffering option.

0x0

R/W

Address: 0x19, Reset: 0x04, Name: REG0019

Figure 127.

Table 64. Bit Descriptions for REG0019

Bits

Bit Name

Description

Reset

Access

[7:6]

CLKOUT2_OP

Programs a Clock Output Buffer Amplitude for Pins CLK2N and CLK2P.

0x0

R/W

00: minimum amplitude, see the Specifications section.

01: see the Specifications section.

10: see the Specifications section.

11: maximum amplitude, see the Specifications section.

[5:4]

CLKOUT1_OP

Programs Clock Output Buffer Amplitude for Pins CLK1N and CLK1P.

0x0

R/W

00: minimum amplitude, see the Specifications section.

01: see the Specifications section.

10: see the Specifications section.

11: maximum amplitude, see the Specifications section.

PD_CLK

Power Down the VCO Multiplexer and Clock Divider.

0x0

R/W

0: active. Normal operation.

1: power-down. Refer to the Block Power Down Control section.

PD_RDET

Power Down the Reference Detector.

0x1

R/W

0: active. Normal operation.

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