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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ADF4377 датащи(PDF) 37 Page - Analog Devices |
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ADF4377 датащи(HTML) 37 Page - Analog Devices |
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37 / 79 page  Data Sheet ADF4377 APPLICATIONS INFORMATION analog.com Rev. 0 | 37 of 79 VCO Automatic Calibration Settings The procedure to determine the SPI registers for an automatic VCO calibration is outlined in the VCO Calibration section. The VCO calibration Step 1 enables the automatic calibration bit, EN_AUTOCAL, along with enabling several VCO calibration dividers, clocks, and the temperature sensor. Table 29. SPI Summary, VCO Automatic Calibration, Step 1 Bit Field Value EN_DNCLK 0x1 EN_DRCLK 0x1 ADC_CLK_SEL 0x0 ADC_A_CONV 0x1 EN_AUTOCAL 0x1 EN_ADC_CNV 0x1 EN_ADC 0x1 EN_ADC_CLK 0x1 PD_ADC 0x0 In VCO calibration Step 2, Table 17 determines the state of CAL_CT_SEL, DCLK_DIV2, and DCLK_MODE based off the 250 MHz PFD frequency. DCLK_DIV1 must always be set to 1 regard- less of PFD frequency. Table 17 provides an equation to calculate fDIV_RCLK fDIV_RCLK=fPFD/2 =250 MHz/2 = 125 MHz Table 30. SPI Summary, VCO Automatic Calibration, Step 2 Bit Field Value CAL_CT_SEL 0x1 DCLK_DIV2 0x0 DCLK_MODE 0x1 DCLK_DIV1 0x1 In the VCO calibration Step 3 and Step 4, Equation 13, Equation 14, Equation 15, and Equation 16 are provided to calculate the SYNTH_LOCK_TIMEOUT bit fields, Bits[14:0], VCO_ALC_TIMEOUT bit fields, Bits[14:0], VCO_BAND_DIV bits, and ADC_CLK_DIV bits from fDIV_RCLK. SYNTH_LOCK_TIMEOUT≥Ceiling 200 μs×125 MHz =25000 VCO_ALC_TIMEOUT≥Ceiling50 μs×125 MHz =6250 VCO_BAND_DIV≥Ceiling 15 μs×125 MHz 16×21 =Ceiling58.59375 =59 ADC_CLK_DIV>Ceiling 125 MHz 400 kHz− 2 4 =Ceiling 77.625 =78 Table 31. SPI Summary, VCO Automatic Calibration, Step 3 and Step 4 Bit Field Value SYNTH_LOCK_TIMEOUT 0x61A8 VCO_ALC_TIMEOUT 0x186A VCO_BAND_DIV 0x3B ADC_CLK_DIV 0x4E Double Buffer and Manual VCO Calibration Settings If multiple frequency settings are desired, double buffering (see the Double Buffering section) and manual programming of the VCO settings can improve frequency switching times. In a single fixed frequency application, such as this design procedure, these modes are rarely required. Therefore, related bits can remain in their power-up default state. Table 32. SPI Summary, Double Buffer and Manual VCO Calibration Settings Bit Field Value M_VCO_CORE 0x0 M_VCO_BAND 0x0 M_VCO_BIAS 0x0 O_VCO_CORE 0x0 O_VCO_BAND 0x0 O_VCO_BIAS 0x0 CLKO_DIV_DB 0x0 DCLK_DIV_DB 0x0 O_VCO_DB 0x0 DEL_CTRL_DB 0x0 SPI Protocol Settings The design goals stated for the SPI protocol (see the Serial Port section) are 1.8 V logic, 4-wire SPI, and optimize SPI write se- quence. REG0000, REG0001, and REG0018 have the SPI related register bits, which are shown in Table 33 with the desired state based on the design goals. The power-on default state is assumed if the bit function is not listed as a design goal. Table 33. SPI Summary - SPI Protocol Bit Field Value CMOS_OV 0x0 SDO_ACTIVE, SDO_ACTIVE_R 0x1 ADDRESS_ASCENSION, AD- DRESS_ASCENSION_R 0x0 SINGLE_INSTRUCTION 0x0 LSB_FIRST, LSB_FIRST_R 0x0 |
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