CS48L32 datasheet(30/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

4.2 Input Signal Path

The CS48L32 input paths can be configured for power-saving operation, ideal for always-on applications. The low-power

configurations allow the power consumption to be optimized with respect to the required audio performance

characteristics.

• If a signal path is configured for analog input, low-power operation can be selected by setting the respective IN1x_

LP_MODE bit.

The analog input path can be configured for mid-power operation by setting INn_OSR = 010. The IN1x_LP_MODE

bit should be cleared in the mid-power configuration. The maximum input-signal level is reduced by 6 dB if

mid-power operation is selected (see Table 3-4); the minimum PGA gain is 6 dB. The mid-power configuration is

deselected by setting INn_OSR = 101.

• If a signal path is configured for digital input, the respective INn_PDMCLK frequency is configured using the INn_

OSR bits. Reducing the INn_PDMCLK frequency reduces power consumption at the expense of audio

performance. The INn_OSR field also supports high performance PDM mode whenever 6.144 MHz INn_PDMCLK

is selected.

If 384 kHz or 768 kHz CLK frequency is selected, the maximum sample rate for the respective paths is restricted

as described in Table 4-1. If the input sample rates are set globally using IN_RATE (i.e., IN_RATE_MODE = 0), all

input paths are affected similarly.

The VOUT_MIC voltage is generated by an internal charge pump and LDO regulator. The MICBIAS1x outputs are derived

from VOUT_MIC; see Section 4.12.

The input signal paths are configured using the fields described in Table 4-3.

Table 4-3. Input Signal Path Configuration

Bit

Label

Default

Description

R16392 (0x4008)

INPUT_RATE_

CONTROL

IN_RATE_

MODE

Input Path Sample Rate Configuration

0 = Global control (all input paths configured using IN_RATE)

1 = Individual channel control (using the respective INnx_RATE fields)

R16416 (0x4020)

INPUT1_

CONTROL1

18:16 IN1_OSR[2:0]

101

Input Path 1 Oversample Rate Control

If analog input is selected, this field is used to select Mid-Power Mode.

010 = Mid Power Mode

101 = Normal

All other codes are reserved

If digital input is selected, this field controls the IN1_PDMCLK frequency.

000 = 384 kHz

001 = 768 kHz

010 = 1.536 MHz

011 = 2.048 MHz

100 = 2.4576 MHz

101 = 3.072 MHz

110 = 6.144 MHz

111 = Reserved

9:8 IN1_PDM_

SUP[1:0]

Input Path 1 PDM Reference Select

Sets the IN1_PDMDATA and IN1_PDMCLK logic levels

00 = VOUT_MIC

01 = MICBIAS1

All other codes are reserved

IN1_MODE

Input Path 1 Mode

0 = Analog input

1 = Digital input

R16420 (0x4024)

IN1L_CONTROL1

29:28 IN1L_SRC[1:0]

Input Path 1 (Left) Source

00 = Differential (IN1LP_1–IN1LN_1)

01 = Single-ended (IN1LP_1)

10 = Differential (IN1LP_2–IN1LN_2)

11 = Single-ended (IN1LP_2)

IN1L_HPF

Input Path 1 (Left) HPF Enable

0 = Disabled

1 = Enabled

IN1L_LP_

MODE

Input Path 1 (Left) Low-Power Mode (applicable to analog input only)

0 = High Performance Mode

1 = Low Power Mode

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