CS48L32 datasheet(39/192 Pages) CIRRUS

39 / 192 page

DS1219F4

Cirrus Logic

CS48L32

4.2 Input Signal Path

The AUXPDM interface signal paths are shown in Fig. 4-13.

Figure 4-13. Auxiliary PDM Interface

The AUXPDM interfaces can be configured in Master or Slave Mode using AUXPDMn_MSTR (where n identifies the

applicable interface 1 or 2). In Master Mode, the clock (CLK) signal is generated by the CS48L32; in Slave Mode, the CLK

signal is an input to the CS48L32.

The CLK frequency is selected using AUXPDMn_FREQ. For each setting of this field, the actual frequency depends on

whether SYSCLK is configured for 48 kHz- or 44.1 kHz-related sample rates. See Section 4.8 for details of the system

clocks. Note that the CLK frequency must be configured in master and slave modes, using the AUXPDMn_FREQ field.

In Slave Mode, the CS48L32 system clock (SYSCLK) must be synchronized to the PDM CLK input. The applicable CLK

must be selected using PDM_FLLCLK_SRC (see Table 4-8) and configured as FLL reference clock using FLL1_

REFCLK_SRC. See Section 4.8 to configure SYSCLK using FLL1 as a clock reference.

Note: If one of the AUXPDM interfaces is configured in Slave Mode, the system clock (SYSCLK) must be synchronized

to the respective CLK input. To operate more than one of these interfaces in Slave Mode concurrently, the

respective interfaces must all be synchronous (i.e., referenced to a common clock source).

ADC

DATA

CLK

IN1LN_1/IN1_PDMCLK

IN1LP_1/IN1_PDMDATA

IN1LP_2

IN1LN_2

IN1RN_1/IN2_PDMCLK

IN1RP_1/IN2_PDMDATA

IN1RP_2

IN1RN_2

DATA

CLK

Auxiliary PDM

Interface 1

AUXPDM1_CLK

AUXPDM1_DOUT

Auxiliary PDM

Interface 2

Digital Mic

Interface

Digital Mic

Interface

Input signal path

IN1L (analog)

IN1L (digital)

IN1R (digital)

IN1R (analog)

IN2L (digital)

IN2R (digital)

AUXPDM2_CLK

AUXPDM2_DOUT

AUXPDM1_SRC[3:0] p. 41

AUXPDM2_SRC[3:0] p. 42

AUXPDM1_DOUT_SRC[3:0] p. 41

AUXPDM2_DOUT_SRC[3:0] p. 41

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