CS48L32 datasheet(97/192 Pages) CIRRUS

97 / 192 page

DS1219F4

Cirrus Logic

CS48L32

4.5 DSP Peripheral Control

4.5.5

Quad SPI Master Interface

The CS48L32 incorporates a quad-SPI master interface, offering flexible capability to support external components such

as flash-memory devices.

4.5.5.1

Overview

The SPI master interface (SPI2) supports high-speed data transfers to/from external components or accessories. It is

ideally suited to controlling flash-memory components. The interface supports four slave-select (SS) outputs and quad

(four-bit) data input/output. High-bandwidth transfers are supported at clock (SCK) frequencies up to 24.576 MHz.

The interface supports write, read, and write-then-read commands, enabling compatibility with a wide variety of control

protocols for external devices. In Host Mode, 64-byte data buffers are used to support continuous transfers (up to 4 MB)

across the external interface. In DMA Mode, the interface transfers data to/from a configurable location within the register

map; circular-buffer operation can be configured, accessing one region of address on a cyclic basis.

4.5.5.2

Interface Configuration

The SPI master interface speed (SCK frequency) is selected using SPI2_SCLK_FREQ_SEL. Clocking for the SPI

interface is derived from SYSCLK, which must be enabled and present whenever the SPI master interface is used. See

Section 4.8 for details of the system clocks.

Note that, depending on the SYSCLK frequency and the available dividers, the actual SCK frequency may differ from the

selected frequency. The SCK frequency, indicated by SPI2_SCLK_FREQ_STS, is the closest available frequency that is

less than or equal to the frequency selection.

The interface supports four slave-select (SS) outputs, enabling multiple devices to be individually accessed on a shared

bus. The active SS output is configured using SPI2_SS_SEL; the selected pin is asserted (Logic 0) at the start of a

transaction and deasserted (Logic 1) at the end. Timing of the SS function is configurable using SPI2_SS_IDLE_DUR and

SPI2_SS_DELAY_DUR as defined in Table 4-34. The SS output can also be asserted by setting SPI2_SS_FRC.

The interface supports selectable phase/polarity control of the clock (SCK) and data (SIO) lines; this is provided using

SPI2_DPHA, SPI2_CPHA, and SPI2_CPOL as described in Table 4-34.

The SPI master interface supports four data pins, SIO0 through SIO3, enabling high-speed transfers in parallel-data

configuration. The interface is configured for one-, two-, or four-bit data using SPI2_SIO_WIDTH. Quad-SPI operation is

supported using four-bit data.

If one-bit data is selected (SPI2_SIO_WIDTH = 0x0), the interface supports either bidirectional data on the SIO0 pin or

separate input/output data connections on SIO0 and SIO1—this is configured using SPI2_3WIRE.

R1167456 (0x11D060)

DSPGP_SET1_LEVEL1

R1167520 (0x11D0A0)

DSPGP_SET2_LEVEL1

R1167584 (0x11D0E0)

DSPGP_SET3_LEVEL1

R1167648 (0x11D120)

DSPGP_SET4_LEVEL1

R1167712 (0x11D160)

DSPGP_SET5_LEVEL1

R1167776 (0x11D1A0)

DSPGP_SET6_LEVEL1

R1167840 (0x11D1E0)

DSPGP_SET7_LEVEL1

R1167904 (0x11D220)

DSPGP_SET8_LEVEL1

15 DSPGP16_SETn_LVL

DSP SETn GPIO16 Output Level

0 = Logic 0, 1 = Logic 1

14 DSPGP15_SETn_LVL

DSP SETn GPIO15 Output Level

13 DSPGP14_SETn_LVL

DSP SETn GPIO14 Output Level

12 DSPGP13_SETn_LVL

DSP SETn GPIO13 Output Level

11 DSPGP12_SETn_LVL

DSP SETn GPIO12 Output Level

10 DSPGP11_SETn_LVL

DSP SETn GPIO11 Output Level

DSPGP10_SETn_LVL

DSP SETn GPIO10 Output Level

DSPGP9_SETn_LVL

DSP SETn GPIO9 Output Level

DSPGP8_SETn_LVL

DSP SETn GPIO8 Output Level

DSPGP7_SETn_LVL

DSP SETn GPIO7 Output Level

DSPGP6_SETn_LVL

DSP SETn GPIO6 Output Level

DSPGP5_SETn_LVL

DSP SETn GPIO5 Output Level

DSPGP4_SETn_LVL

DSP SETn GPIO4 Output Level

DSPGP3_SETn_LVL

DSP SETn GPIO3 Output Level

DSPGP2_SETn_LVL

DSP SETn GPIO2 Output Level

DSPGP1_SETn_LVL

DSP SETn GPIO1 Output Level

Table 4-33. DSP GPIO Control (Cont.)

Bit

Label

Default

Description

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