CS48L32 datasheet(16/192 Pages) CIRRUS

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Cirrus Logic

DS1219F4

CS48L32

3 Characteristics and Specifications

Table 3-16. Audio Serial Port—Slave Mode

The following timing information is valid across the full range of recommended operating conditions, unless otherwise noted.

Parameter 1,2

1.Audio serial port timing—Slave Mode. Note that BCLK and FSYNC

inputs can be inverted if required; the figure shows the default,

noninverted polarity.

2.If ASPn_BCLK or ASPn_FSYNC is selected as a source for SYSCLK (either directly or via the FLL), the frequency must be within 1% of the

SYSCLK_FREQ setting.

Symbol Min Typ Max Units

ASPn_BCLK cycle time

tBCY

—

ASPn_BCLK pulse width high

BCLK as direct SYSCLK source

All other conditions

tBCH

—

ASPn_BCLK pulse width low

BCLK as direct SYSCLK source

All other conditions

tBCL

—

CLOAD = 15 pF (output pins),

BCLK slew (10%–90%) = 3 ns

ASPn_FSYNC set-up time to BCLK rising edge

tLRSU

7—

—

ASPn_FSYNC hold time from BCLK rising edge

tLRH

0—

—

ASPn_DOUT propagation delay from BCLK falling edge

tDD

0— 13.6

ASPn_DIN set-up time to BCLK rising edge

tDSU

2—

ASPn_DIN hold time from BCLK rising edge

tDH

0—

Master FSYNC, ASPn_FSYNC propagation delay from BCLK falling edge

tLRD

—— 12.2

CLOAD = 25 pF (output pins),

BCLK slew (10%–90%) = 6 ns

ASPn_FSYNC set-up time to BCLK rising edge

tLRSU

7—

ASPn_FSYNC hold time from BCLK rising edge

tLRH

0—

ASPn_DOUT propagation delay from BCLK falling edge

tDD

0— 14.7

ASPn_DIN set-up time to BCLK rising edge

tDSU

2—

ASPn_DIN hold time from BCLK rising edge

tDH

0—

Master FSYNC, ASPn_FSYNC propagation delay from BCLK falling edge

tLRD

—— 13.4

Note: The descriptions above assume noninverted polarity of ASPn_BCLK.

BCLK

(input)

FSYNC

(input)

DOUT

(output)

DIN

(input)

tDSU

tDD

tDH

tLRH

tLRSU

tBCH

tBCL

tBCY

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