CS48L32 datasheet(40/192 Pages) CIRRUS

40 / 192 page

Cirrus Logic

DS1219F4

CS48L32

4.2 Input Signal Path

The input source for each AUXPDM interface is selected using AUXPDMn_SRC and AUXPDMn_DOUT_SRC.

• If analog input is selected (AUXPDMn_DOUT_SRC = 0x0), the respective input path and ADC are enabled

automatically. Note that the mute and digital-volume settings of the IN1 path have no effect on the AUXPDM output.

The AUXPDM interface is enabled by setting AUXPDMn_EN. Note that the other AUXPDM control fields should be

configured before enabling the interface; the AUXPDMn_EN bit should be set as the final step of the

AUXPDM-enable sequence. The AUXPDMn_EN bit should be cleared before changing the interface configuration.

Note that, in Master Mode, the clock output is undriven (high-impedance) if the AUXPDM interface is disabled; the

clock output is enabled by setting AUXPDMn_EN. Integrated pull-down resistors can be enabled on the clock pins

as described in Section 4.2.11.

The output signal can be muted and unmuted using AUXPDMn_MUTE. The timing of the data (DOUT) signal can

be controlled using AUXPDMn_TXEDGE—this selects whether DOUT changes on the rising or falling edge of CLK.

The auxiliary PDM interface timing is shown in Fig. 4-14 (assuming analog input is selected). In Master Mode, the

clock and data outputs are driven synchronously by the CS48L32. In Slave Mode, the timing of the output data is

controlled by the external clock input. See Table 3-14 for timing information.

Figure 4-14. Auxiliary PDM Interface Timing (Analog Input Source)

• If digital input is selected (AUXPDMn_DOUT_SRC = 0x1 or 0x2), the respective INn_PDMDATA signal is passed

directly to the AUXPDM data output pin— note that the interface can pass either mono or stereo data in this case.

If IN1_PDMDATA is selected as source, IN1_MODE must be set and one or both of IN1L/IN1R must be enabled. If

IN2_PDMDATA is selected as source, one or both of IN2L/IN2R must be enabled.

Note that the AUXPDM interface _EN, _MUTE, and TXEDGE control fields have no effect if digital input is selected.

The auxiliary PDM interface timing needs to be considered in combination with the DMIC/PDM input path timing, if

digital input is selected as the AUXPDM source. The associated signals are subject to propagation delays between

the DMIC/PDM interface and the AUXPDM interface, as described in Table 3-14.

— The AUXPDMn_DATA output is sourced directly from the INn_PDMDATA input.

— In AUXPDM Master Mode, the INn_PDMCLK and AUXPDMn_CLK outputs are generated from SYSCLK. In

AUXPDM Slave Mode, the INn_PDMCLK output is sourced directly from the AUXPDMn_CLK input.

Aux PDM clock

Aux PDM data

(AUXPDMn_TXEDGE = 0)

Aux PDM data

(AUXPDMn_TXEDGE = 1)

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