CS48L32 datasheet(90/192 Pages) CIRRUS

90 / 192 page

Cirrus Logic

DS1219F4

CS48L32

4.5 DSP Peripheral Control

If SYSCLK is selected as the source, a lower clocking frequency can be configured using TIMERn_REFCLK_FREQ_SEL

field (if TIMERn_REFCLK_SRC = 0x8) or TIMERn_DSPCLK_FREQ_SEL field (if TIMERn_REFCLK_SRC = 0x0). The

applicable division ratio is determined automatically, assuming the SYSCLK frequency has been correctly configured as

described in Section 4.8.

Note that, depending on the SYSCLK frequency and the available clock dividers, the timer reference frequency may differ

from the frequency configured by TIMERn_DSPCLK_FREQ_SEL. In most cases, the timer reference equals or exceeds

the requested frequency; a lower frequency is implemented if limited by either the SYSCLK frequency or the maximum

TIMERn clocking frequency.

If TIMERn_REFCLK_SRC > 0x0, the clock source can be further divided using TIMERn_REFCLK_DIV. Division ratios in

the range 1 to 128 can be selected.

The reference frequency (after TIMERn_REFCLK_FREQ_SEL, TIMERn_DSPCLK_FREQ_SEL, and TIMERn_REFCLK_

DIV) must be compatible with the following constraints:

• The reference frequency must be less than 12 MHz, and close to 50% duty cycle

• If SYSCLK is enabled, the reference frequency must be less than SYSCLK / 3

One final division, controlled by TIMERn_PRESCALE, determines the timer count frequency. This field is valid for all clock

reference sources; division ratios in the range 1 to 128 can be selected. The output from this division corresponds to the

frequency at which the TIMERn_COUNT field is incremented (or decremented).

The maximum count value of the timer is determined by TIMERn_MAX_COUNT. This is the final count value (if counting

up), or the initial count value (if counting down). The current value of the timer counter can be read from the TIMERn_

CUR_COUNT field.

The timer is started by writing 1 to TIMERn_START. Note that, if the timer is already running, it restarts from its initial value.

The timer is stopped by writing 1 to TIMERn_STOP. The count direction (up or down) is selected using TIMERn_DIR.

The TIMERn_CONT bit selects whether the timer automatically restarts after the end-of-count condition has been reached.

The TIMERn_RUNNING_STS bit indicates whether the timer is running, or if it has stopped.

Note that the timer should be stopped before making any changes to the timer control registers. The timer configuration

should only be changed if TIMERn_RUNNING_STS = 0.

4.5.3.3

Interrupts and GPIO Output

The timer status is an input to the interrupt control circuit and can be used to trigger an interrupt event after the final count

value is reached—see Section 4.9. Note that the interrupt does not occur immediately when the final count value is

reached; the interrupt is triggered at the point when the next update to the timer count value would be due.

The timer status can be output directly on a GPIO pin as an external indication of the timer activity. See Section 4.10 to

configure a GPIO pin for this function.

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