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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS48L32 датащи(PDF) 13 Page - Cirrus Logic |
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CS48L32 датащи(HTML) 13 Page - Cirrus Logic |
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13 / 192 page  13 Cirrus Logic DS1219F4 CS48L32 3 Characteristics and Specifications Table 3-12. System Clock and Frequency-Locked Loop (FLL) The following timing information is valid across the full range of recommended operating conditions. Parameter Minimum Typical Maximum Units Master clock timing (MCLK1) 1 1.If MCLK1 is selected as a source for SYSCLK (either directly or via the FLL), the frequency must be within 1% of the SYSCLK_FREQ setting. MCLK cycle time MCLK as input to FLL, FLL1_REFCLK_DIV = 00 MCLK as input to FLL, FLL1_REFCLK_DIV = 01 MCLK as input to FLL, FLL1_REFCLK_DIV = 10 MCLK as input to FLL, FLL1_REFCLK_DIV = 11 MCLK as direct SYSCLK source 77 38 19 12.5 20 — — — — — — — — — — ns ns ns ns ns MCLK duty cycle MCLK as input to FLL MCLK as direct SYSCLK source 80:20 60:40 — — 20:80 40:60 % % Frequency-locked loop (FLL1) FLL input frequency FLL1_REFCLK_DIV = 00 FLL1_REFCLK_DIV = 01 FLL1_REFCLK_DIV = 10 FLL1_REFCLK_DIV = 11 0.032 0.064 0.128 0.256 — — — — 13 26 52 80 MHz MHz MHz MHz Internal clocking SYSCLK frequency SYSCLK_FREQ = 000, SYSCLK_FRAC = 0 SYSCLK_FREQ = 000, SYSCLK_FRAC = 1 SYSCLK_FREQ = 001, SYSCLK_FRAC = 0 SYSCLK_FREQ = 001, SYSCLK_FRAC = 1 SYSCLK_FREQ = 010, SYSCLK_FRAC = 0 SYSCLK_FREQ = 010, SYSCLK_FRAC = 1 SYSCLK_FREQ = 011, SYSCLK_FRAC = 0 SYSCLK_FREQ = 011, SYSCLK_FRAC = 1 SYSCLK_FREQ = 100, SYSCLK_FRAC = 0 SYSCLK_FREQ = 100, SYSCLK_FRAC = 1 –1% –1% –1% –1% –1% –1% –1% –1% –1% –1% 6.144 5.6448 12.288 11.2896 24.576 22.5792 49.152 45.1584 98.304 90.3168 +1% +1% +1% +1% +1% +1% +1% +1% +1% +1% MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz Table 3-13. Digital Input (PDM/DMIC) Interface Timing The following timing information is valid across the full range of recommended operating conditions. Parameter 1 1.PDM/DMIC interface timing Symbol Minimum Typical Maximum Units INn_PDMCLK cycle time tCY 160 163 1432 ns INn_PDMCLK duty cycle — 45 — 55 % INn_PDMCLK rise/fall time (25 pF load, 1.8 V supply) tr, tf 5 — 30 ns INn_PDMDATA (left) setup time to falling PDMCLK edge tLSU 15 — — ns INn_PDMDATA (left) hold time from falling PDMCLK edge tLH 0— — ns INn_PDMDATA (right) setup time to rising PDMCLK edge tRSU 15 — — ns INn_PDMDATA (right) hold time from rising PDMCLK edge tRH 0— — ns Note: The voltage reference for the DMIC interfaces is selectable, using the INn_PDM_SUP fields—each interface may be referenced to VOUT_MIC or MICBIAS1. (left data) (right data ) INn_PDMDATA (input) VIL VIH tRH tRSU tLH tLSU VL INn_PDMCLK (output) tCY VH tr tf |
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