CS48L32 datasheet(76/192 Pages) CIRRUS

76 / 192 page

Cirrus Logic

DS1219F4

CS48L32

4.4 DSP Firmware Control

4.4.3.1

DSP Memory

The DSP firmware memory comprises program memory (P-memory) and data memory (X-memory and Y-memory) as

described in Section 4.4.2. Each memory (X, Y, or P) is arranged as a number of banks; the banked configuration enables

each memory to support multiple simultaneous read/write accesses.

Each bank of memory can be individually enabled or disabled; the power consumption of the firmware memory can be

optimized by enabling only the banks that are required for a particular application.

The CS48L32 firmware memory also supports a low-power retention state; in this state, the memory contents are retained,

but read/write access is not supported. The low-power retention state is selectable for each memory region (P, X, or Y),

and applies to all enabled banks of the respective memory.

The DSP firmware memory is controlled using the x_PWD_N and x_EXT_N_n fields described in Table 4-27. Separate

controls are provided for odd-numbered and even-numbered words within each memory region.

• x_PWD_N selects the active or data-retention state for the respective memory. In the active state, read/write access

is supported. In the data-retention state, the memory contents are maintained, but read/write access is not possible.

• x_EXT_N_n selects the enabled or disabled state for the respective memory bank n. If the bank is disabled, the

contents are lost. If the bank is enabled, read/write access is supported (provided the respective memory is active).

The memory-control fields are summarized in Table 4-26.

Notes: If a memory bank is disabled, the contents of this bank are lost—the low-power retention state is not valid for

disabled memory banks. The memory is not actively cleared in the disabled state—some contents of the memory

may persist in the disabled state, but the integrity of the memory contents is not assured.

If a memory bank is disabled, all higher-numbered banks in the same memory (X, Y, or P) are unavailable. It is

recommended to disable the higher-numbered banks by clearing the respective x_EXT_N_n bits.

The DSP memory-control fields are not affected by software reset; these bits remain in their previous state under

software-reset conditions. The DSP firmware memory contents are maintained through software reset, provided

the respective memory bank is enabled.

The DSP1 memory-control fields are defined in Table 4-27.

Table 4-26. DSP Memory Control

x_PWD_N

x_EXT_N_n

Description

Memory disabled, contents lost

Memory enabled in data-retention state

Memory disabled, contents lost

Memory enabled for read/write access

Table 4-27. DSP Memory Control Registers

Bit

Label

Default

Description

R94220 (0x1700C)

DSP1_XM_SRAM_IBUS_SETUP_0

DSP1_XM_SRAM_IBUS_E_PWD_N

X-memory even-address power control

0 = Data-retention state

1 = Memory active

Only valid for enabled memory banks

DSP1_XM_SRAM_IBUS_O_PWD_N

X-memory odd-address power control

0 = Data-retention state

1 = Memory active

Only valid for enabled memory banks

R94224 (0x17010)

DSP1_XM_SRAM_IBUS_SETUP_1

R94316 (0x1706C)

DSP1_XM_SRAM_IBUS_SETUP_24

DSP1_XM_SRAM_IBUS_E_EXT_N_n

X-memory even-address Bank n enable

0 = Disabled

1 = Enabled

DSP1_XM_SRAM_IBUS_O_EXT_N_n

X-memory odd-address Bank n enable

0 = Disabled

1 = Enabled

CS48L32 датащи(PDF) 76 Page - Cirrus Logic

CS48L32 датащи(HTML) 76 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL