CS48L32 datasheet(74/192 Pages) CIRRUS

74 / 192 page

Cirrus Logic

DS1219F4

CS48L32

4.4 DSP Firmware Control

Status registers describing the Halo Core DSP are provided within the CS48L32 register map, as shown in Table 4-24.

The default values of these fields are provided in Section 6.

Trace buffer

• Trace buffer depth

• Trace stack depth

Yes

Watchdog timer

Yes

Interrupt controller

Yes

Stream arbiter

• Number of receive channels

• Number of transmit channels

• Number of master controllers

• Number of interrupt generators

• Data width—integer part

• Data width—fractional part

Yes

4 bits

31 bits

AHB bus master

Yes

Memory protection unit

Yes

Memory controller

• Number of X-memory banks

• Number of Y-memory banks

• Number of P-memory banks

• Number of boot-memory banks

Yes

Table 4-24. DSP Configuration Definition

Bit

Label

Description

DSP1 base address = 0x200_0000

base address + 0x5E_0000

DSPn_SYS_INFO_ID

31:0

DSPn_SYS_ID[31:0]

DSP identifier

base address + 0x5E_0004

DSPn_SYS_INFO_VERSION

31:0

DSPn_SYS_VERSION[31:0]

DSP version number

base address + 0x5E_0008

DSPn_SYS_INFO_CORE_ID

31:0

DSPn_SYS_CORE_ID[31:0]

DSP instance

base address + 0x5E_000C

DSPn_SYS_INFO_AHB_ADDR

31:0

DSPn_SYS_AHB_BASE_ADDR[31:0] DSP start address in the device register map

base address + 0x5E_0010

DSPn_SYS_INFO_XM_SRAM_SIZE

31:0

DSPn_SYS_XM_SRAM_SIZE[31:0]

X-memory size (number of 24-bit words)

base address + 0x5E_0018

DSPn_SYS_INFO_YM_SRAM_SIZE

31:0

DSPn_SYS_YM_SRAM_SIZE[31:0]

Y-memory size (number of 24-bit words)

base address + 0x5E_0020

DSPn_SYS_INFO_PM_SRAM_SIZE

31:0

DSPn_SYS_PM_SRAM_SIZE[31:0]

P-memory size (number of 20-bit words)

Note this includes the boot memory, if present.

base address + 0x5E_0028

DSPn_SYS_INFO_PM_BOOT_SIZE

31:0

DSPn_SYS_PM_BOOT_SIZE[31:0]

Boot-memory size (number of 20-bit words)

base address + 0x5E_002C

DSPn_SYS_INFO_FEATURES

DSPn_SYS_SELF_BOOT

1 = DSP supports self-boot on release from reset

DSPn_SYS_DB_RAND_EXISTS

1 = DSP provides dB/linear conversion

DSPn_SYS_LMS_EXISTS

1 = DSP provides LMS filters

DSPn_SYS_FIR_EXISTS

1 = DSP provides FIR filters

DSPn_SYS_FFT_EXISTS

1 = DSP provides FFT accelerator

9DSPn_SYS_MIPS_EXISTS

1 = DSP provides MIPS profiler

8DSPn_SYS_TRB_EXISTS

1 = DSP provides trace buffer

7DSPn_SYS_WDT_EXISTS

1 = DSP provides watchdog timer

5DSPn_SYS_STREAM_ARB_EXISTS

1 = DSP provides stream arbiter control

4DSPn_SYS_AHBM_EXISTS

1 = DSP provides AHB bus master

3DSPn_SYS_MPU_EXISTS

1 = DSP provides MPU function

base address + 0x5E_0030

DSPn_SYS_INFO_FIR_FILTERS

5:0

DSPn_SYS_NUM_FIR_FILTERS[5:0] Number of FIR filters

Table 4-23. Halo Core DSP Definition (Cont.)

Description

DSP1

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