CS48L32 datasheet(29/192 Pages) CIRRUS

29 / 192 page

DS1219F4

Cirrus Logic

CS48L32

4.2 Input Signal Path

4.2.5

Input Signal Path Sample-Rate Control

The input signal paths may be selected as input to the digital mixers or signal-processing functions within the CS48L32

digital core. The sample rate for the input signal paths can be set globally, or can be configured independently for each

input channel.

The IN_RATE_MODE bit (defined in Table 4-3) controls whether the input sample rates are set globally using IN_RATE,

or independently for each input channel using the INnx_RATE fields (where n is 1–2 and x is L or R for the left/right

channels respectively). The IN_RATE and INnx_RATE fields are defined in Table 4-21.

Note that sample-rate conversion is required when routing the input signal paths to any signal chain that is configured for

a different sample rate.

4.2.6

Input Signal Path Configuration

The CS48L32 supports up to four analog inputs or up to four digital inputs. Selectable combinations of analog (mic or line)

and digital inputs are multiplexed into two stereo input signal paths:

• Input path IN1 can be configured for single-ended, differential, or digital (PDM) operation. The analog input

configuration and pin selection is controlled using the IN1x_SRC bits; digital input mode is selected by setting IN1_

MODE.

• Input path IN2 supports digital inputs only, using the respective IN2_PDMCLK and IN2_PDMDATA pins.

Note: The external pin connections for IN2 are shared with the IN1R analog input paths. If IN2L or IN2R input paths are

enabled, the IN1R analog input is restricted to differential (IN1RP_2–IN1RN_2) or single-ended (IN1RP_2)

configurations only.

A configurable high-pass filter (HPF) is provided on the left and right channels of each input path. The applicable cut-off

frequency is selected using IN_HPF_CUT. The filter can be enabled on each path independently using the INnx_HPF bits.

The analog input signal paths (single-ended or differential) each incorporate a PGA to provide gain in the range 0 dB to

+31 dB in 1 dB steps. The analog input PGA gain is controlled using IN1L_PGA_VOL and IN1R_PGA_VOL. Note that the

PGAs do not provide pop suppression; it is recommended that the gain should not be adjusted if the respective signal path

is enabled.

If digital input mode is selected, the respective PDM clock (INn_PDMCLK) is generated by the CS48L32. The frequency

is controlled by INn_OSR.

If a signal path is configured for digital input, the voltage reference for the associated input/output pins is selectable using

INn_PDM_SUP—each interface may be referenced to VOUT_MIC or MICBIAS1. For DMIC use cases, the voltage

reference for each input path should be set equal to the power supply of the respective microphones.

Note: When writing to IN1_MODE, INn_OSR, or INn_PDM_SUP, take care not to change other nonzero bits that are

configured at the same register address. Bit [5] should be set at all times.

R16388 (0x4004)

INPUT_STATUS

IN2L_STS

Input Path 2 (left) enable status

0 = Disabled

1 = Enabled

IN2R_STS

Input Path 2 (right) enable status

0 = Disabled

1 = Enabled

IN1L_STS

Input Path 1 (left) enable status

0 = Disabled

1 = Enabled

IN1R_STS

Input Path 1 (right) enable status

0 = Disabled

1 = Enabled

Table 4-2. Input Signal Path Enable (Cont.)

Bit

Label

Default

Description

CS48L32 датащи(PDF) 29 Page - Cirrus Logic

CS48L32 датащи(HTML) 29 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL