L9966 datasheet(43/122 Pages) STMICROELECTRONICS

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Figure 20. SYNC controlled sequencer example

GADG0801181212PS

The input voltage on SYNC is evaluated with a comparator, see Table 26. The digital signal after the comparator

is filtered for time duration tSYNC-glitch before triggering the sequencer. The trigger event is a rising edge on filtered

SYNC pulse.

Table 26. SYNC pin parameters

Symbol

Parameter

Condition

Min

Typ

Max

Unit

UBSW = 7.5 V:36 V, VDD5V = 4.85 V:5.15 V, Tj-max = 150 °C unless otherwise specified.

VinH

SYNC input high level

1.7

2.3

SYNC

VinL

SYNC input low level

1.2

1.4

SYNC

Vhys

SYNC input hysteresis

0.23

0.6

SYNC

tSYNC-glitch

SYNC input filter time

4.2

4.7

5.2

µs

SYNC

RPD

SYNC input pull-down

105

150

kΩ

SYNC

9.2.3

Priority mechanism

The two EUx work in parallel with shared resources (ADC resistance and ADC voltage). The EU has access to

the selected ADC as soon as it is no more engaged by the other EU or the SC. In case more than one EU has a

request to the same ADC, the ADC manager applies the following priority rules:

•

Priority HIGH: Single Conversion Module

•

Priority MEDIUM: Execution Unit 1

•

Priority LOW: Execution Unit 2

In case of continuous loop programmed, EU1 loses its priority for one clock cycle every time its sequence is

completed (that means INT is generated, see Section 9.3 Interrupt generation) and Figure 21 INT_EU1 in

SQNCR_INT_MSK_FLG is set leaving to EU2 the opportunity to proceed with an eventual pending request on

ADC_x.

Table 27 and Figure 21 report an example of ADC priority management in case of conflict in the access to one

ADCx through the sequencer flow:

EU1 performs CH1, CH2 CH3, CH4 voltage conversion, then points back to CH1 and generates the interrupt.

EU2 performs resistance measurement on CH11, CH12, voltage measurement on VI5V, VIX then points back to

CH11 and generates the interrupt.

SC voltage measurement on CH5 occurs while EU1 is running.

At cursor 1, EU1 completes the sequence and thus loses priority for one clock cycle. In that moment, neither EU2

nor SC are requesting ADC1, then EU1 restarts the sequence with CH1 conversion right after.

At cursor 2, EU2 has already completed ADC2 conversions on CH11 and CH12 and has a pending request

for ADC1. As soon as EU1 ends the sequence, EU2 can take over, performing ADC1 conversion on VI5V. At

conversion end, EU1 regains priority and restarts with CH1.

L9966

Sequencer

DS12459 - Rev 10

page 43/122

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