L9966 datasheet(26/122 Pages) STMICROELECTRONICS

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6.3

Control of current source

For IO[4:1] if R20K_SENT_x =0 the control of current source is as reported below; if R20K_SENT_x =1, the

internal current sources are kept off and the internal R = 20 kΩ pull up is connected to VDD5.

Figure 13. IOx configuration diagram

GADG0501181224PS

For each input, the correspondent current source is driven according to CURR_SRC_CTRL_x register in the

following ways:

CV[2:0] bits define the current source value

CIS[3:0] bits define which signal controls the IOx current source configuration.

In case CIS[3:0] = 0000, no comparator is used as reference and the channel being set is controlled as always

having a low level input.

In case CIS[3:0] = IOy, different from the IOx, IOy status (defined by its input comparator) selects the direction

of the current source, according to SEL[2:0] and MODE bit setting. If the current source (IOx) is controlled by

another IOy, the delay time depends on whether pull up or pull down voltage is set.

In case of pull up to VDD5 the delay is 5V_REF_dly, in case of pull up to VVAR the delay is VVAR_dly, as

specified in Table 13.

In case CIS[3:0] selects the same channel being set (e.g. CIS[3:0] = 0011 and x = 3), an auxiliary source is

selected: either the VRS or CTRL_CFG pins control the current source on channel x, based on AUX_Even/Odd

channel bit in register SWITCH_ROUTE.

L9966

Control of current source

DS12459 - Rev 10

page 26/122

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