L9966 datasheet(56/122 Pages) STMICROELECTRONICS

56 / 122 page

In the 16-bit instruction a “start” register address is present. As long as the CS signal keeps low and the SCLK is

running, 16-bit data is either sampled on MOSI line (write access) or shifted out on MISO line (read access). The

next register gets selected automatically after each 16 clock cycles on SCLK. In case of write access after each

complete 16 SCLK cycles the data is written into the register, no input buffer present.

A correct SCLK cycles number check is done after CS rising: the SCLK count must be a multiple of 16*(m+1)

where m is the number of frames transferred during the burst mode. During burst, each valid 16-bit word is

considered as data and latched inside the addressed register: eventually, if the last bits sent on SPI bus don't

belong to a packet of 16 bits, these are discarded, see Figure 30. Burst mode error handling. In case of a parity

error within one of the 16 SCLK transmissions, the following part of the burst will be completely rejected, including

the wrong frame. These two errors (too many bits or parity errors) set the TRANS_F bit at the next SPI transfer.

Figure 30. Burst mode error handling

16 bit instruction

16 bit data

Check Byte

zz + 14 bit

previous register

content

too less data

previous register

content

…..

store data

reject data

check correct number

of SCLK cycles (16+m*16)

CLK

SPI parity error in a frame inside the burst

SPI invalid address in a frame inside the burst

CS_N

MISO

MOSI

VR_EN

PARITY_OK

data

instruction

CLK

CS_N

MISO

RD_EN

MOSI

ACCESS ADDRESS

data

instruction

check byte

address + 0

address + 1 (not present)

check byte

data @address

address + 2

data @address + 2

0xFFFF

write operation

parity check fall - write operation cancelled

write operation cancelled

fetch register at address +2

write operation cancelled

fetch register at address +0

GADG1001181525PS

When the instruction is initialized with an invalid address, the whole SPI access is invalidated and TRANS_F flag

bit is set at the next SPI transfer.

As it is shown in the picture, it is allowed to perform a SPI burst operation with incremental address going through

an invalid address. Operation on not existing register is discarded.

Note:

When burst mode is not active (SPI CLK_MON=1), a write SPI access composed by 16 bit valid instruction

word + 16*(1+2k) valid data word (k > 0) does not flag TRANS_F bit. The frame is recognized as valid and a

command composed by the first 16 instruction bit + the last 16 data bit is issued.

L9966

Burst mode

DS12459 - Rev 10

page 56/122

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