L9966 datasheet(47/122 Pages) STMICROELECTRONICS

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SENT Interface

FlexInput implements 4 channels to filter SENT signals and provides them to an external decoder through

SENTx_GTMx x=1:4 output pins. The output buffers are push-pull. IO[4:1] inputs are configured as analog input

at the power-up. SENTx_GTMx are configured either as SENT or GTM via the SWITCH_ROUTE register. At

power up IO15 is routed on SENT4_GTM4 in GTM mode, while the other SENTx_GTMx outputs are kept in HiZ.

When a whatever pin of IO[4:1] is configured as SENT through SWITCH_ROUTE register, the corresponding

SENTx_GTMx buffer is automatically programmed in SENT mode and an eventual previous configuration as GTM

is overwritten.

This function includes a 2-stage filter and the possibility to connect a pull-up input structure.

Externally a matching impedance net is required as reported in Figure 25 and Table 28. The SENT input and filter

circuitry fulfil SAE J2716 Rev. 4 standard requirements.

To fulfil SAE J2716 input stage of each IOx x=1:4 is equipped with an internal resistor (RPU) of 20kohm

connected to VDD5. The RPU can be independently connected to the IOx via SPI command, through 20kPU_x,

x=1:4 bit in GTM_TO_SENT_ROUTE_x_y register.

In case 20kPU_x bit is set, the IOx configuration defined in CURR_SRC_CTRL_x, x=1:4 is reset to the default

value: CV[2:0]=000, CV_DW[1:0]=00, SEL[2:0]=000. MODE=0 and CIS[3:0]=0000. The correspondent IO is

consequently tight to VDD5 through the internal 20kohm; the current flowing through the IO depends on the

external load.

In this configuration, current through the IO is limited both in case of short to ground or short to UBSW.

The modification on 20kPU_x bit set, from ‘1’ to ‘0’, determines the reset at default value of any previous

configuration in CURR_SRC_CTRL_x related to the IOx whose 20kPU_x bit was reset.

Digital sampling may be disabled by reg GTM_TO_SENT_ROUTE_1_2 bit[10:11] and

GTM_TO_SENT_ROUTE_3_4 bit[10:11]. In this way no digital sampling will effect output signal.

Figure 25. SENT input structure

GADG1001180813PS

Table 28. SENT interface electrical parameters

Symbol

Parameter

Condition

Min

Typ Max Unit

UBSW = 7.5 V:36 V, VDD5V = 4.85 V:5.15 V, Tj-max = 150 °C unless otherwise specified.

Stage1tau

First stage time constant

0.74

1.73

µs

IO1-4

Stage2tau

Second stage time constant

0.6

1.4

µs

IO1-4

VoL

Output low voltage

Iload = |2 mA|

0.5

SENT1-4

VoH

Output high voltage

Iload = |2 mA|

VDD5-0.5

SENT1-4

tSENT-rise

Output rise time (100 pF load)

From 20% to 80%, design

info

SENT1-4

tSENT-fall

Output fall time (100 pF load)

From 80% to 20% design info

SENT1-4

tdist

Distorsion time

Difference between delay (IO

→SENTx) in the rising and

falling edge with fast analog

filter

2.95

µs

SENT1-4

L9966

SENT Interface

DS12459 - Rev 10

page 47/122

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