L9966 datasheet(42/122 Pages) STMICROELECTRONICS

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SPI readout

New measurement

data available

Copy command effect

No readout

Yes

Copy of buffer content (with new data)

NEW_RESULT flag set

Readout

Overwrite SPI register with buffer content (same data)

NEW_RESULT flag not set

Readout

Yes

Copy of buffer content (with new data)

NEW_RESULT flag set

9.2.2

Sequencer execution control

Sequencer starting phase is defined in SQNCR_CTRL register through EUx_EN or EUx_SYNC_EN bit:

•

EUx_EN = ‘1’ allows sequencer starting (see Section 9.2.3 Priority mechanism for conflict management);

EUx_EN = ‘0’ stops the correspondent EUx as soon as the running ADC conversion is completed.

•

EUx_SYNC_EN = ‘1’ allows correspondent EUx starting synchronous with the rising edge of the external

SYNC signal. In case SYNC rising edge occurs while the sequencer is running, SYNC toggle is ignored.

In case of open loop sequence, once the specific EUx is over, EUx_EN bit is automatically reset; EUx_EN bit is

otherwise always kept enabled.

Execution flows steps:

The execution unit EUx is started by setting the run bit EUx_EN=’1’ (by SPI command or by SYNC).

Following steps run only if EUx_EN bit is kept to ‘1’, otherwise the correspondent EUx will stop without

asserting the INT pin to flag the end of conversion.

As a first step, the EUx reads the control data on register SQNCR_CTRL.

The EUx waits for the requested ADC to be available.

The EUx sets the ADC according to the configuration written in the first SQNCR_CMDx being chosen.

The EUx starts the ADC conversion and waits till the conversion is finished.

The EUx moves the ADC data to the internal buffer result register corresponding to the pointed channel.

The EUx reads the next buffer line address (SQNCR_CMDx). If the sequencer is configured to run closed

sequences, the EUx starts over with step 2, else it stops.

If not masked (register SQNCR_INT_MSK_FLG), an interrupt is generated on INT pin each time a closed

sequence starts over or the ENDLOOP condition occurs (see Section 9.3 Interrupt generation).

Once running, the sequencer is not stopped abruptly. If EUx_EN are asynchronously written to zero the eventual

ADCx ongoing conversion is completed then the execution unit EUx stops with no INT assertion.

In Figure 20 a possible scenario of sequencer being controlled by the SYNC pin is shown.

Before starting the sequencer, both EU1 and EU2 are configured to be triggered by the SYNC pin.

As soon as the filtered SYNC pulse rising edge is detected, both EUx start.

SYNC pulse occurs while both EUx are running -> SYNC toggle ignored.

SYNC pulse occurs when EU1_EN has reached its ENDLOOP condition (EU1_EN=0) whereas EU2 is still

running -> EU1 starts a new loop, EU2 ignores the SYNC toggle.

SYNC pulse is detected once both EUs have completed their sequence -> both start a new run.

EU1 and EU2 are stopped via SPI, writing EU1_EN, EU2_EN and EU1_SYNC_EN to ‘0’. Being

EU2_SYNC_EN set, a new SYNC toggle starts EU2 only.

EU1_SYNC_EN is set again: next SYNC toggle restarts EU1, while EU2 keeps on running.

L9966

Sequencer

DS12459 - Rev 10

page 42/122

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