L9966 datasheet(45/122 Pages) STMICROELECTRONICS

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EU1 requires ADC1 to measure IO1 and IO2 in loop and INT_EU1_CONF=IO1

•

EU2 requires ADC1 to measure IO3 and IO4 in loop and INT_EU2_CONF=IO3

Both EUx are enabled through SYNC signal and both are in LOOP (the last command line points back to the first

one).

As SYNC pin rises, EU2 starts performing ADC1 conversion on IO3 while EU1 waits for the yield. At the end of

the conversion, EU1 gains priority and starts running with IO1. Once EU1 loop is completed, it loses priority for

one clock cycle, EU2 can take over, performing ADC1 conversion on IO4. The procedure runs up to EUx_EN is

forced 0.

Figure 23. Example of sequencer priority case

Every time the sequencer starts with an ADC conflict in the first line, EU2 takes the priority then the mechanism

proceeds as described in the above scenarios.

9.3

Interrupt generation

Every time an EUx/SC loop reaches an interrupt condition, a pulse on INT pin can be generated.

EU_x/SC interrupt on INT pin can be masked by writing corresponding CFG_EU[2:1]/CFG_SC to ‘1’ in the

SQNCR_INT_MSK_FLG.

As the interrupt is asserted, a flag is set on INT_EU[2:1]/INT_SC on the SQNCR_INT_MSK_FLG; such a flag is

not masked by CFG_EU[2:1]/CFG_SC and gets cleared after being read.

Interrupt condition

Provided that no interrupt mask is enabled, the conditions that can lead to the generation of the interrupt are the

following.

For EUx, there are two possible cases: open loop and closed loop condition. In open loop condition, EUx

completes the last step conversion then points to ENDLOOP determining the interrupt generation, as shown

in A next figure. In closed loop condition instead, INT generation depends on what is programmed in

INT_EUx_CONF[3:0] field of the SQNCR_INT_MSK_FLG register.

Note:

INT_EUx_CONF are write only fields, any read back returns 0000.

INT is generated every time EUx has processed the SQNCR_CMD_x line whose NEXT_PC points to the same

line selected in INT_EUx_CONF[3:0] field, as shown in B and C of the following figure.

Figure 24. Interrupt condition open/closed loop INT generation

GADG0901181543PS

INIT_PC_EU1 = 1

SQNCR_CMD_1 NXT_PC=2

SQNCR_CMD_2 NXT_PC=3

SQNCR_CMD_3 NXT_PC=4

SQNCR_CMD_4 NXT_PC=5

SQNCR_CMD_5 NXT_PC=6

SQNCR_CMD_6 NXT_PC=0

INT pin

INT_EU1

INIT_PC_EU1 = 1

INT_EU1_CONF = 3

INIT_PC_EU1 = 1

INT_EU1_CONF = 5

SQNCR_CMD_1 NXT_PC=2

SQNCR_CMD_2 NXT_PC=3

SQNCR_CMD_3 NXT_PC=4

SQNCR_CMD_4 NXT_PC=5

SQNCR_CMD_5 NXT_PC=6

SQNCR_CMD_6 NXT_PC=3

INT pin

INT_EU1

SQNCR_CMD_1 NXT_PC=2

SQNCR_CMD_2 NXT_PC=3

SQNCR_CMD_3 NXT_PC=4

SQNCR_CMD_4 NXT_PC=5

SQNCR_CMD_5 NXT_PC=6

SQNCR_CMD_6 NXT_PC=3

INT pin

INT_EU1

L9966

Interrupt generation

DS12459 - Rev 10

page 45/122

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