L9966 datasheet(33/122 Pages) STMICROELECTRONICS

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ADC converter

Two sigma delta time continuous converters are implemented.

ADC1(VOLT) is a general purpose 1.25 V full scale, 12 bits ∑∆ converter used for input voltage measurement

while ADC2(RES) is a dedicated 15 bits ∑∆ converter used for resistance measurement function on the 12

FlexInput analog input pins.

It is possible to access to ADC resource in two different ways: in single conversion mode (SC) or through a

sequential approach (sequencer), which is equipped with 2 execution units (EU1, EU2).

A new conversion can be requested once the running conversion is completed. In case the condition is violated

the algorithm can be blocked and a reset (hardware or software) is required to re-engage the procedure.

Should either IOx settings or ADCx configuration change while conversion is running, the first result after the new

setting is unreliable: configuration registers are not locked.

ADC_TIMING register is used to configure settling time both for voltage and for resistance measurements. The

settling time step resolution is respectively 8 μs for voltage measurement and 200 μs for resistance measurement.

Resistance measurement settling time is selectable independently for each of the RRx reference pins.

Once a single conversion or a complete sequencer cycle ends, an interrupt pulse can be generated on INT pin (if

not masked). The behaviour of INT pin is defined in the register SQNCR_INT_MSK_FLG over the bit CFG_EU2,

CFG_EU1 and CFG_SC. Bits INT_EU2, INT_EU1, INT_SC indicate flag which unit generated the interrupt, also

in case the interrupt on INT pin is masked.

In order to avoid any noise injection on the internal nets that impacts the accuracy both for ADC1 and ADC2, no

ratiometric comparator has to be connected on the IOx where the ADCs measurement is on going. To be noted

that ratiometric comparator sweeps through all channels but it is effectively connected only to the IOx which have

been selected for UTh_ratio.

No problem instead if the absolute comparators are used (see Section 12 Voltage comparators).

In case CALIB_FLT=1 in GEN_STATUS register, it is recommended to disable the calibration, that means

configure CALIB_SEL=0 in the same register.

8.1

ADC1: voltage measurement

Purpose of this ADC is to achieve voltage measurement over all the 12 analog input pins, 3 ECU internal voltage

monitors (UBSW, VI5V, VIX), internal junction temperature, internal BandGap and 3 digital input pins.

The ADC circuitry implements an input time-continuous filtering structure intended to filter out HF noise and to

avoid aliasing effects, see Table 21.

Table 21. ADC analog constant time

Symbol

Parameter

Condition

Min

Typ

Max

Unit

UBSW = 7.5 V:36 V, VDD5V = 4.85 V:5.15 V, Tj-max = 150 °C unless otherwise specified.

ADC1tau_1_4_low ADC input analog filter constant time

SENTx_GTM_ROUTEx=0x0

and RSENTx=0

-45%

4.4

+45%

µs

IO1-4

ADC1tau_1_4_high ADC input analog filter Tau for SENT config

SENTx_GTM_ROUTEx≠0x0

or RSENTx≠0

-40.1%

1.235

+40.1%

µs

IO1-4

ADC1tau_5_12

ADC input analog filter constant time

-45%

4.20

+45%

µs

IO5-12

ADC1tau_13_15

ADC input analog filter constant time

-50%

8.4

+50%

µs

IO13-15

ADC1df

ADC input analog filter damping factor

20dB/dec

IO1-15

The FlexInput also implements different input voltage dividers to adapt the ADC to different input ranges. The

input impedance of the channel is strongly dependent on the selected full-scale.

L9966

ADC converter

DS12459 - Rev 10

page 33/122

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