L9966 datasheet(60/122 Pages) STMICROELECTRONICS

60 / 122 page

In case of ratiometric comparator selected for one or more IOx, the ratiometric comparator sweeps between all

IOx with a total sweeping time of T_cycle, see Section 12.2 Ratiometric comparator; the IOx digital conversion is

updated every T_cycle time.

In case of absolute comparators, each IOx has a dedicated absolute comparator, the IOx digital conversion is

immediately updated.

In both cases SENTx_GTMx is the result of the IOx comparison with the threshold selected, that in turn is

reported for each IO in DIG_IN_STAT register, as described in Section 12 Voltage comparators.

When SENTx_GTMx is not assigned to any channel (SENTx_GTM_ROUTE_x=0), the output pin is in HiZ.

Table 42. SENTx_GTMx electrical parameters

Symbol

Parameter

Condition

Min

Typ Max Unit

UBSW = 7.5 V:36 V, VDD5V = 4.85 V:5.15 V, Tj-max = 150 °C unless otherwise specified.

SENToutH

Output high level

Iload = |2 mA|

VDD5-0.5

SENTx/GTMx

SENToutL

Output low level

Iload = |2 mA|

0.5

SENTx/GTMx

SENTout_HiZ Tri-state impedance

>1M

Ω

SENTx/GTMx

Delay time HL

Delay time rising edge

(covered by filter time test)

IOx as per default config; IOx routed on GTMy

µs

SENTx/GTMx

Delay time LH

Delay time falling edge

(covered by filter time test)

IOx as per default config; IOx routed on GTMy

µs

SENTx/GTMx

In case one or more IO[4:1] are configured as SENT, output of signal processing chains are automatically

routed on SENTx_GTMx regardless of any possible existing configuration in GTM_TO_SENT_ROUTE_1_2 or

GTM_TO_SENT_ROUTE_3_4.

In case of IO1:4, it is possible to:

•

select the fast or slow filter through AN_FIL_x in GTM_TO_SENT_ROUTE_x_y register

•

Insert or not the 1 μs digital filter through DIG_FIL_x in SWITCH_ROUTE register

•

route the absolute comparator output directly on SENTx_GTMx through DIG_BP_x in

GTM_TO_SENT_ROUTE_x_y register, in this case no digital sampling is performed.

14.3

INT output

The INT output pin is used to generate an interrupt in order to flag the end of single conversion or

the end of command list programmed for both EU1 and EU2 (NEXT_PC either reached END LOOP or

INT_EUx_CONF[3:0]). INT flag is managed through SQNCR_INT_MSK_FLG register: it is possible to selectively

enable / disable the toggle on INT pin while the flag generation is never inhibited.

Output Type: Push-pull, see Table 43. INT electrical parameters.

Table 43. INT electrical parameters

Symbol

Parameter

Condition

Min

Typ

Max

Unit

UBSW = 7.5 V:36 V, VDD5V = 4.85 V:5.15 V, Tj-max = 150 °C unless otherwise specified.

INToutH

Output high level

Iload = |2 mA|

VDD5-0.5

INT

INToutL

Output low level

Iload = |2 mA|

0.5

INT

INTtoggle

INT toggle time

-9%

+9%

µs

INT

14.4

WAKE output

The WAKE output pin and WAK_UP_FLG are set high at the end of Power up cycle, as showed in

Figure 5. Operating mode state diagram.

L9966

INT output

DS12459 - Rev 10

page 60/122

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