L9966 datasheet(16/122 Pages) STMICROELECTRONICS

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Symbol

Parameter

Condition

Min

Typ

Max

Unit

IVDD5REF

VDD5REF

NORMAL mode

100

µA

VDD5REF

MAIN_OSC

NORMAL mode oscillator frequency

-9%

+9% MHz

LOW_SPEED_OSC LOW SPEED OSC

SLEEP mode low power, low speed oscillator

frequency

-40%

+40% MHz

NVM_timeout

NVM timeout

Guaranteed by design

-40% 3.125 +40%

5.6.1

Software reset

Configuration bit can be cleared by entering RST_ACTIVE mode, or alternatively, by issuing a SOFT_RESET

command procedure. The procedure is a sequence of 3 separate SPI write operations with activation codes

specified in the register description in Section 16.18 SOFT_RST_CMD. Only consecutive write accesses are

allowed: any write or read access in-between will reset the activation code. After procedure completion the device

moves back in NORMAL mode.

5.7

Chip status

The status of the chip can be read in the GEN_STATUS register. In particular CFG_CHK[1:0] bit in GEN_STATUS

are configured to default ‘10’ after power-up. User can write any different code during NORMAL mode to

understand later if a new POR or a reset event has occurred (POLLING does not impact these two bits).

The device is equipped with an overtemperature protection that could be masked. When not masked, as soon

as the overtemperature is detected, the OT_FLT bit sets to ‘1’ and the device goes to the FAULT mode. When

masked setting OT_MASK = ‘1’, the fault bit is set, but the device will not enter FAULT mode.

Overtemperature diagnostic is active at power up after trimming bits have been downloaded from internal

EEPROM; in case a fault of the download procedure is detected, such a function is disabled and an eventual

overtemperature is not detected.

An internal voltage comparator is implemented on the internal supply reference (3V3_ref) to monitor its proper

range. In case of fault, the 3V3_FLT bit is set and the device goes to the FAULT mode. Once the fault is no longer

persisting and the bit is read, the bit itself is cleared.

At the POWER up, as soon as UBSW is recognized higher than VPOR, the device downloads the EEPROM

content; the internal FSM, before reaching the WAKE state, waits until 3V3_FLT is de-asserted. Once the

EEPROM content has been downloaded into the internal registers, a consistency check of data is performed;

result of this check is CALIB_FLT, which takes into account an eventual fault of calibration data for ADC1 and

ADC2, and TRIM_FLT flag, which takes into account the consistency of data used for trimming.

When UBSW falls down, once 3V3_FLT is asserted, the analog section is no more guaranteed to properly

operate. Bandgap reference, main oscillator, voltage monitoring, logic section (SYNC, RST, INT) and SPI keep

working allowing the possibility to read the internal status of 3V3 signal. Internal current generators, VRS, GTM,

AOX blocks are switched off; the configuration is still kept until UBSW goes below VPOR, that generates a POR

event.

Parameters that determine fault condition for the device are defined in Table 9.

Table 9. Chip status electrical parameters

Symbol

Parameter

Condition

Min Typ Max Unit

UBSW = 7.5 V:36 V, VDD5V = 4.85 V:5.15 V, Tj-max = 150 °C unless otherwise specified.

VPOR

POR threshold H to L

Battery POR threshold

2.5

UBSW

POR threshold L to H

Battery POR threshold

Design info

4.5

UBSW

3V3_FLTh

3V3_FLT higher threshold,

By design

If internal 3V3 > 3V3_FLTh => 3V3_FLT = ‘0’; POR is not

activated

Design info

2.8

3.2

UBSW

L9966

Chip status

DS12459 - Rev 10

page 16/122

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