FS5502 datasheet(92/113 Pages) NXP

92 / 113 page

NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

27.3.2 Fault error counter

The FS5502 integrates a configurable fault error counter that counts the number of faults

related to the device itself and also caused by external events. The fault error counter

starts at level 1 after a POR or resuming from Standby. The final value of the fault error

counter is used to transition in DEEP-FS mode. The maximum value of this counter is

configurable with the FLT_ERR_CNT_LIMIT[1:0] bits during the INIT_FS phase.

FLT_ERR_CNT_LIMIT[1:0]

Fault error counter max value configuration

01 (default)

Reset condition

POR

Table 89. Fault error counter configuration

27.4 PGOOD, RSTB

These two output pins have a hierarchical implementation in order to guarantee the safe

state.

• PGOOD has the priority one. If PGOOD is asserted, RSTB is asserted.

• RSTB has the priority two. If RSTB is asserted, PGOOD may not be asserted.

27.4.1 PGOOD

PGOOD is an open-drain output that can be connected in the application to the PORB of

the MCU. PGOOD requires an external pull-up resistor to VDDIO and a filtering capacitor

to GND for immunity. An internal pull-down RPD ensures PGOOD low level in Standby

and Power down mode. VCOREMON, VDDIO, VMON1 can be assigned to PGOOD by

OTP.

PGOOD is asserted low by the FS_LOGIC when any of the assigned regulators are in

undervoltage or overvoltage. When PGOOD is asserted low, RSTB is also asserted low.

An internal pull up on the gate of the low-side MOS ensures PGOOD low level in case of

FS_LOGIC failure.

aaa-031028

FS_LOGIC

VSUP

PGOOD

to MCU PORB

VDDIO

RPD

5.1 kΩ

1 nF

Figure 35. PGOOD pin implementation

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

92 / 113

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