FS5502 datasheet(72/113 Pages) NXP

72 / 113 page

NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

aaa-033203

20 MHz INT. OSC

(SPREAD SPECTRUM,

FREQ TUNING)

enable

CLK2

CLK1

PLL x 48

out

DIVIDER

/48

DIVIDER 2

/44 (OTP)

PHASE

SHIFTING

FOUT_clk

VPRE_clk

BUCK1,3_clk

FOUT

PHASE

SHIFTING

FIN

VDDI2C

DIVIDER

/1, /6

CLK_FIN_DIV

MONITORING

OSC_MAIN/48

CLK_FIN_DIV

EXT_FIN_SEL

EXT_FIN_DIS

Vddio

FOUT_MUX_SEL

FOUT_clk

VPRE_clk

BUCKs_clk

CLK_FIN_DIV

OSC_Main/48

OSC_FS/48

DIVIDER 1

/9 (OTP)

OTP:

PLL_SEL

Figure 23. Clock management block diagram

18.2 Phase shifting

The clocks of the switching regulators (VPRE_clk, BUCK1_clk and BUCK3_clk) can be

delayed in order to avoid all the regulators to turn ON at the same time to reduce peak

current and improve EMC performance.

Each clock of each regulator can be shifted from 1 to 7 clock cycles of CLK

running at 20 MHz what corresponds to 50 ns. The phase shift configuration is

done by OTP configuration using OTP_VPRE_ph[2:0], OTP_BUCK1_ph[2:0] and

OTP_BUCK3_ph[2:0].

VPRE and BUCK3 have a peak current detection architecture. The PWM synchronizes

the turn ON of the high-side switch. BUCK1 has a valley current detection architecture.

The PWM synchronizes the turn ON of the low-side switch.

18.3 Manual frequency tuning

The internal oscillator frequency, 20 MHz by default, can be programmed from 16 MHz

to 24 MHz with 1.0 MHz frequency step by I2C. The oscillator functionality is guaranteed

for frequency increment of one step at a time in either direction, with a minimum of 10

μs between two steps. For any unused code of the CLK_TUNE [3:0] bits, the internal

oscillator is set at the default 20 MHz frequency.

To change the internal oscillator frequency from 20 MHz to 24 MHz, four I2C commands

are required with 10 μs wait time between each command (21 MHz – wait 10 μs – 22

MHz – wait 10 μs – 23 MHz – wait 10 μs – 24 MHz). To change the internal oscillator

frequency from 24 MHz to 16 MHz, eight I2C commands are required with 10 μs wait time

between each command (23 MHz – wait 10 μs – 22 MHz – wait 10 μs – 21 MHz – wait

10 μs – 20 MHz – wait 10 μs – 19 MHz – wait 10 μs – 18 MHz – wait 10 μs – 17 MHz –

wait 10 μs – 16MHz).

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

72 / 113

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