FS5502 datasheet(60/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

14.7 VPRE not populated

When two FS5502 are used, only one VPRE may be required. It is possible to not

populate the external components of the second VPRE to optimize the bill of material.

In that case, specific connection of the VPRE2 pins is required:

• PRE_FB2 must be connected to PRE_FB1

• PRE_CSP2 must be connected to PRE_FB1

• PRE_COMP2 must be left open

• PRE_SW2 must be connected to GND

• PRE_BOOT2 must be connected to VBOS2

• PRE_GHS2 and PRE_GLS2 must be left open

After the startup phase, VPRE2 shall be disabled by I2C with VPDIS bit.

15 Low voltage buck: BUCK1

15.1 Functional description

BUCK1 block is low voltage, synchronous, valley current mode buck converters with

integrated HS PMOS and LS NMOS. BUCK1 works in force with PWM. The output

voltage is configurable by OTP from 0.8 V to 1.8 V, the switching frequency is 2.22

MHz and the output current is limited to 3.6 A peak. The input of these blocks must

be connected to the output of VPRE. The stability is ensured by an internal Type 2

compensation network with slope compensation.

By default, BUCK1 switching frequency is derived from the internal oscillator and can

be synchronized with an external frequency signal applied on FIN input pin. The change

from internal oscillator to external clock or vice versa is controlled by I2C.

An overcurrent detection and a thermal shutdown are implemented on BUCK1 to protect

the internal MOSFETs. The overcurrent induces a duty cycle reduction that could lead to

the output voltage gradually dropping, causing an undervoltage condition.

The ramp up and ramp down of BUCK1 when they are enabled and disabled is

configurable with OTP_DVS_BUCK1[1:0] bits to accommodate multiple MCU soft

start requirements. Static Voltage Scaling (SVS) feature is available to decrease the

output voltage after power up during INIT_FS. Programmable phase shift control is

implemented, see Section 18 "Clock management".

15.2 Application schematic: Single phase mode

In this configuration, BUCK1 output is configured and controlled independently by I2C.

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

60 / 113

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