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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FS5502 датащи(PDF) 45 Page - NXP Semiconductors |
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FS5502 датащи(HTML) 45 Page - NXP Semiconductors |
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45 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO Address Register Bit Symbol Value Description VBUCK3 phase (delay) selection 000 no delay 001 delay 1 010 delay 2 011 delay 3 100 delay 4 101 delay 5 110 delay 6 26 OTP_CFG_CLOCK_3 5 to 3 BUCK3_ph[2:0] 111 delay 7 BUCK3 clock selection 7 BUCK3_clk_sel 0 CLK_DIV1 = 2.22 MHz BUCK2 clock selection 6 BUCK2_clk_sel 0 CLK_DIV1 = 2.22 MHz BUCK1 clock selection 5 BUCK1_clk_sel 0 CLK_DIV1 = 2.22 MHz VBOOST clock selection 4 VBST_clk_sel 0 CLK_DIV1 = 2.22 MHz VPRE clock selection 0 CLK_DIV1 = 2.22 MHz 3 VPRE_clk_sel 1 CLK_DIV2 = 455 kHz PLL enable 0 Disabled 27 OTP_CFG_CLOCK_4 2 PLL_sel 1 Enabled conf_TSD[5] RESERVED BUCK1 behavior in case of TSD 0 BUCK1 shutdown conf_TSD[4] 1 BUCK1 shutdown + DFS conf_TSD[3] RESERVED BUCK3 behavior in case of TSD 0 BUCK3 shutdown conf_TSD[2] 1 BUCK3 Shutdown + DFS LDO1 behavior in case of TSD 0 LDO1 shutdown conf_TSD[1] 1 LDO1 shutdown + DFS 28 OTP_CFG_SM_1 5 to 0 conf_TSD[0] RESERVED Delay to turn OFF VPRE at device power down 0 250 μs 4 VPRE_off_dly 1 32 ms Synchronization with 1x FS5502 or 1x PF82 0 2x FS5502 1 PSYNC_CFG 1 1x FS5502 and 1x PF82 Synchronization with two devices 0 Disabled 29 OTP_CFG_SM_2 0 PSYNC_EN 1 Enabled Table 59. Main OTP bit description...continued FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 45 / 113 |
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