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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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FS5502 датащи(PDF) 79 Page - NXP Semiconductors |
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FS5502 датащи(HTML) 79 Page - NXP Semiconductors |
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79 / 113 page  NXP Semiconductors FS5502 High voltage PMIC with multiple SMPS and LDO TA = −40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground. Symbol Parameter Min Typ Max Unit PSYNCVIH High level input voltage threshold — — 2 V PSYNCHYST Hysteresis 0.1 — — V PSYNCVOL Low level output threshold (I = 2.0 mA) — — 0.5 V PSYNCIPD Internal pull-down current source 7 10 13 μA PSYNCRPU External pull-up resistor to VBOS — 10 — kΩ PSYNCCOUT External decoupling capacitor — 0.1 — μF PSYNCTFB Feedback filtering time 6 10 15 μs Table 74. PSYNC electrical characteristics...continued 20 I2C interface 20.1 I2C interface overview The FS5502 use an I2C interface following the high-speed mode definition up to 3.4 Mbit/ s. I2C interface protocol requires a device address for addressing the target IC on a multi- device bus. The FS5502 has two device address: one to access the main logic and one to access the fail-safe logic. These two I2C addresses are set by OTP. The I2C interface is using a dedicated power input pin VDDI2C and it's compatible with 1.8 V / 3.3 V input supply. Timing, diagrams, and further details can be found in the NXP I2C specification UM10204 rev6. B39 B38 B37 B36 B35 B34 B33 B32 B31 B30 B29 B28 B27 B26 B25 B24 ID_6-0 0 0 0 Adr_5-0 Device address Read/Write Register address B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 Data_15 Data_14 Data_13 Data_12 Data_11 Data_10 Data_9 Data_8 Data_7 Data_6 Data_5 Data_4 Data_3 Data_2 Data_1 Data_0 Data MSB Data LSB B7 B6 B5 B4 B3 B2 B1 B0 CRC_7 CRC_6 CRC_5 CRC_4 CRC_3 CRC_2 CRC_1 CRC_0 CRC_7 CRC_6 CRC_5 CRC_4 CRC_3 CRC_2 CRC_1 CRC_0 Table 75. I2C message arrangement 20.2 Device address The FS5502 has two device address: one to access the Main logic and one to access the Fail-safe logic. B39 B38 B37 B36 B35 B34 B33 0 1 OTP OTP OTP OTP M/FS The I2C addresses have the following arrangement: • Bit 39: 0 • Bit 38: 1 • Bit 37 to 34: OTP value • Bit 33: 0 to access the main logic, 1 to access the fail-safe logic FS5502 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 4 — 27 October 2021 79 / 113 |
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