FS5502 datasheet(52/113 Pages) NXP

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NXP Semiconductors

FS5502

High voltage PMIC with multiple SMPS and LDO

13.2 Best of supply electrical characteristics

TA = –40 °C to 125 °C, unless otherwise specified. VSUP = VSUP_UVH to 36 V, unless otherwise specified. All voltages referenced to ground.

Symbol

Parameter

Min

Typ

Max

Unit

VBOS

Best of supply output voltage

3.3

5.0

5.25

VBOS_UVH

VBOS undervoltage threshold high (VBOS rising)

4.1

—

4.5

VBOS_UVL

VBOS undervoltage threshold low (VBOS falling)

3.2

—

3.4

TBOS_UV

VBOS_UVH and VBOS_UVL filtering time

6.0

μs

VBOS_POR

VBOS power on reset threshold

—

2.5

TBOS_POR

VBOS_POR filtering time

0.5

—

1.5

μs

IBOS

Best of supply current capability

—

Effective output capacitor

4.7

—

µF

COUT_BOS

Output decoupling capacitor

—

0.1

—

µF

Table 61. Best of supply electrical characteristics

14 High voltage buck: VPRE

14.1 Functional description

VPRE block is a high voltage, synchronous, peak current mode buck controller. VPRE

is working with external logical level NMOS in force PWM mode at 455 kHz and in

Automatic Pulse Skipping (APS) mode at 2.22 MHz. The APS mode helps to maintain

the correct output voltage at high input voltage by skipping some turn ON cycles of the

HS FET below the minimum duty cycle. VPRE input voltage is naturally limited to VSUP =

LPI_DCR x IPRE + VPRE_UVL / DMAX with DMAX = 1 – (FPRE_SW x TPRE_OFF_MIN). A bootstrap

capacitor is required to supply the gate drive circuit of the high-side NMOS. The output

voltage is configurable by OTP from 3.3 V to 5.0 V, and the switching frequency is

configurable by OTP at 455 kHz for 12 V and 24 V transportation applications or 2.22

MHz for 12 V automotive applications. The stability is ensured by an external Type 2

compensation network with slope compensation.

The output current is sensed via an external shunt in series with the inductor and

the maximum current capability is defined by the external components (NMOS gate

charge, inductor, shunt resistor), the gate driver current capability and the switching

frequency. An overcurrent detection is implemented to protect the external MOSFETs. If

an overcurrent is detected after the HS minimum TON time, the HS is turned OFF and

will be turned ON again at the next rising edge of the switching clock. The overcurrent

induces a duty cycle reduction that could lead to the output voltage gradually dropping,

causing an undervoltage condition on VPRE and/or one of the cascaded regulators.

The maximum input voltage is 60 V and allows operation in 24 V truck applications

without external protection to sustain ISO 16750-2:2012 load dump pulse 5b. VPRE must

be the input supply of the BUCK1. VPRE can be the input supply of BUCK3 and LDO1.

VPRE can be the supply of local loads remaining inside the ECU.

By default, VPRE switching frequency is derived from the internal oscillator, and can be

synchronized with an external frequency signal applied at FIN input pin. The change from

internal oscillator to external clock or vice versa is controlled by I2C.

VPRE_UVH, VPRE_UVL and VPRE_FB_OV thresholds are monitored from PRE_FB pin and

manage some transitions of the main state machine described in Section 8.1 "Simplified

functional state diagram".

FS5502

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4 — 27 October 2021

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