ATXP032 datasheet(25/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

continues reading the same line until all bytes of the first line have been read out once. In the next clock cycle, the

device starts reading at the beginning of the next line as shown in Section 8-7. The device reads continuously as

long as SCK is clocked. There is no delay caused by the wrap-around, the first byte of the cache line follows

immediately after the last. There is also no additional delay caused by the jump to the next cache line, the first byte

of the following cache line follows immediately after the last byte read from the previous one, independent of where

in the cache line the jump is coming from.

Figure 8-7.

Burst Read with Wrap, Continuous Mode (W7 = 1)

An example of this operation in continuous mode is shown in Figure 8-8. As in the above example, the wrap length

is set to 8, and the requested address is 1E34h. The device reads 1E34h first, followed by 1E35h, 1E36h, and

1E37h. It then wraps around, and the next address to be read out is 1E30h, followed by 1E31h, 1E32h, and 1E33h.

If the read operation continues, the device will then output 1E38h, followed by 1E39h and so on. The device reads

continuously as long as the device is clocked.

Figure 8-8.

Burst Read with Wrap Example, Continuous Mode (W7 = 1), Wrap Length 8, Requested Address = 1E34h

If the MCU does not immediately need or cannot immediately handle the next cache line after the first one has

finished, it can stop the clock while keeping the CS line low. It can resume clocking once it is ready to receive the

next cache line. This of course assumes the MCU does not need to issue any other commands to the memory

device between receiving the two cache lines.

The value of the I/O lines while the clock is stopped depend on the value of the clock:

If the clock is stopped high in SDR mode, the I/O lines output the value of the last byte of the previous cache line.

The entire byte is output in octal mode.

If the clock is stopped low in SDR mode, the I/O lines output the value of the first byte of the next cache line. The

entire byte is output in octal mode.

If the clock is stopped high in DDR mode, the I/O lines output the value of the first byte of the next cache line. The

entire byte is output in octal mode.

If the clock is stopped low in DDR mode, the I/O lines output the value of the last byte of the previous cache line.

The entire byte is output in octal mode.

Byte 0

Note: Each transition

shown represents one byte (8 bits)

Byte N

First Byte

Read

Byte N +1

Address

Requested

Note: Each transition

shown represents one byte (8 bits)

1E30

1E31

1E32

1E33

1E34

1E35

1E36

1E37

1E38

1E39

1E40

1E41

1E42

1E43

1E44

1E45

First Byte

Read

Address

Requested

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