ATXP032 datasheet(71/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Figure 12-8. Write Status Registers in Octal Mode — SDR

Figure 12-9. Write Status Registers in Octal Mode — DDR

12.8

Write Status Register Byte 1 (01h)

The Write Status Register Byte 1 (01h) command is used to modify the SPRL bit of the Status/Control register

and/or to perform a global protect or global unprotect operation. Before the Write Status Register command can be

issued, the Write Enable command must have been previously issued to set the WEL bit in the Status/Control

To issue the Write Status Register command, the CS pin must first be asserted and the command of 01h must be

clocked into the device followed by one byte of data. The one byte of data consists of the SPRL bit value, a don’t

care bit, four data bits to denote whether a global protect or unprotect operation should be performed, and two

additional don’t care bits (see Table 12-12). Any additional data bytes that are sent to the device are ignored.

When the CS pin is deasserted, the SPRL bit in the Status/Control register is modified, and the WEL bit in the

Status/Control register is reset back to a logic “0”. The values of bits 5, 4, 3, and 2 and the state of the SPRL bit

before the Write Status Register command was executed (the prior state of the SPRL bit) determines whether or

not a global protect or global unprotect operation is performed. See Section 10.5, Global Protect/Unprotect on

page 47 for more details.

The complete one byte of data must be clocked into the device before the CS pin is deasserted; otherwise, the

device aborts the operation, the state of the SPRL bit does not change, no potential global protect or unprotect is

performed, and the WEL bit in the Status/Control register is reset back to the logic “0” state.

If the WP pin is asserted, then the SPRL bit can only be set to a logic “1”. If an attempt is made to reset the SPRL

bit to a logic “0” while the WP pin is asserted, then the Write Status Register command is ignored, and the WEL bit

Byte1

Byte2

Data

A7-0

Address

71h

Opcode

I/O7-0

SCK

Input Data

Byte1 Byte2 Byte3

Address

Bits A

-A

71h

Opcode

I/O7-0

SCK

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