ATXP032 datasheet(51/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Essentially, if the SPRL bit of the Status/Control register is in the logic “0” state (Sector Protection registers are not

locked), then writing a 00h to the Status/Control register performs a global unprotect without changing the state of

the SPRL bit. Similarly, writing a 7Fh to the Status/Control register performs a global protect and keeps the SPRL

bit in the logic “0” state. The SPRL bit can, of course, be changed to a logic “1” by writing an FFh if software-locking

or hardware-locking is desired along with the global protect.

If the desire is to only change the SPRL bit without performing a global protect or global unprotect, then the system

can write a 0Fh to the Status/Control register to change the SPRL bit from a logic “1” to a logic “0” provided the WP

pin is deasserted. Likewise, the system can write an F0h to change the SPRL bit from a logic “0” to a logic “1”

without affecting the current sector protection status (no changes will be made to the Sector Protection registers).

When writing to the Status/Control register, bits 5, 4, 3, and 2 are not actually modified, but are decoded by the

device for the purposes of the Global Protect and Global Unprotect functions. Only bit 7, the SPRL bit, is actually

modified. Therefore, when reading the Status/Control register, bits 5, 4, 3, and 2 do not reflect the values written to

them but instead indicate the status of the WP pin and the sector protection status. Please refer to the Read Status

values can be read for bits 5, 4, 3, and 2.

10.6

Read Sector Protection Registers (3Ch)

The Sector Protection registers can be read to determine the current software protection status of each sector.

Reading the Sector Protection registers, however, does not determine the status of the WP pin.

To execute a Read Sector Protection Register command for a particular sector, the CS pin must first be asserted

and the 3Ch command must be clocked in. Once the command has been clocked in, four address bytes

designating any address within the sector must be clocked in. After the last address byte has been clocked in, the

device begins outputting data on the SO pin during every subsequent clock cycle. The data being output is a

repeating byte of either FFh or 00h to denote the value of the appropriate Sector Protection register.

0 x 0 0 0 0 x x

0 x 0 0 0 1 x x

⁞

0 x 1 1 1 0 x x

0 x 1 1 1 1 x x

1 x 0 0 0 0 x x

1 x 0 0 0 1 x x

⁞

1 x 1 1 1 0 x x

1 x 1 1 1 1 x x

No change to the current protection level. All sectors currently

protected will remain protected, and all sectors currently unprotected

will remain unprotected.

The Sector Protection Registers are soft-locked and cannot be

changed when the current state of SPRL is 1. Therefore, a Global

Protect/Unprotect will not occur. However, the SPRL bit can be

changed back to a 0 from a 1 since the WP pin is HIGH. To perform a

Global Protect/Unprotect, the Write Status Register command must

be issued again after the SPRL bit has been changed from a 1 to a 0.

Table 10-2. Valid SPRL and Global Protect/Unprotect Conditions (Continued)

State

Current

SPRL

Value

New

Write Status

Protection Operation

New

SPRL

Value

Bit

7 6 5 4 3 2 1 0

Table 10-3. Read Sector Protection Register – Output Data

Output Data

Sector Protection Register Value

00h

Sector Protection Register value is 0 (sector is unprotected).

FFh

Sector Protection Register value is 1 (sector is protected).

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