ATXP032 datasheet(22/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Note that for DDR operation in octal mode, all read operations operate on an even number of bytes. The minimum

number of SCK pulses for clocking data is one, and as data is clocked on both edges, two bytes are read. Address

bit A

0 has to be always 0 in this mode to ensure correct alignment of the two bytes read or written. If address bit A0

is set to 1, it is ignored and treated as A

0 = 0 by the device.

After the address bytes (and the dummy bytes if using command 0Bh) have been clocked in, additional clock

cycles result in data being output on the I/O pin(s). The data is always output with the MSB of a byte first. When the

last byte (3FFFFFh) of the memory array has been read, the device continues reading back at the beginning of the

array (000000h). No delays are incurred when wrapping around from the end of the array to the beginning of the

array.

Deasserting the CS pin terminates the read operation and put the I/O pins into high-impedance state. The CS pin

can be deasserted at any time and does not require a full byte of data be read.

Figure 8-1.

Read Array with 3-byte Address — 03h Command

Figure 8-2.

Read Array — 0Bh Command

MSB

LSB

MSB

Output Data Byte 1

Address Bits A23-A0

Opcode

10 11

32 33

36 37

29 30

SCK

MSB

LSB

MSB

Output Data Byte 1

Dummy Byte

Address Bits A31-A0

Opcode

10 11

48 49

52 53

37 38

41 42

45 46

SCK

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