ATXP032 datasheet(59/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

12.1.1 SPRL Bit

The SPRL bit is used to control whether the Sector Protection registers can be modified or not. When the SPRL bit

is in the logic “1” state, all Sector Protection registers are locked and cannot be modified with the Protect Sector

and Unprotect Sector commands (the device ignores these commands). In addition, the global protect and global

unprotect features cannot be performed. Any sectors that are presently protected remain protected, and any

sectors that are presently unprotected remain unprotected.

When the SPRL bit is in the logic “0” state, all Sector Protection registers are unlocked and can be modified (the

Protect Sector and Unprotect Sector commands, as well as the global protect and global unprotect features, are

processed as normal). The SPRL bit defaults to the logic “0” state after a power-up or a device reset.

The SPRL bit can be modified freely whenever the WP pin is deasserted. However, if the WP pin is asserted, then

the SPRL bit may only be changed from a logic “0” (Sector Protection registers are unlocked) to a logic “1” (Sector

Protection registers are locked). In order to reset the SPRL bit back to a logic “0” using the Write Status Register

command, the WP pin will have to first be deasserted. The SPRL bit is the only bit of the Status/Control register

that can be user modified via the Write Status Register command.

12.1.2 DPDS Bit

The DPDS bit is used to detect if the device is in deep power-down mode or not. This bit reads 1 if in DPD or

UDPD, 0 in any other mode. To differentiate between DPD and UDPD, check the value of the UDPDS Bit.

12.1.3 EPE Bit

The EPE bit indicates whether the last erase or program operation completed successfully or not. If at least one

byte during the erase or program operation did not erase or program properly, then the EPE bit is set to the logic

“1” state. The EPE bit is not set if an erase or program operation aborts for any reason such as an attempt to erase

or program a protected region or if the WEL bit is not set prior to an erase or program operation. The EPE bit is

updated after every erase and program operation.

The EPE bit reflects the correct state after an erase or program operation if read upon P/E completion, before

executing another erase or program command or an Ultra-Deep Power-Down (79h) command.

The EPE bit reflects the correct state after erase or program with Auto Deep Power-Down Mode after a Program or

Erase Operation, if exit from UDPD is done with JEDEC Standard Hardware Reset (In-Band Reset) or Hardware

Reset and the EPE bit is read before executing another erase or program command or an Ultra-Deep Power-Down

(79h) command.

WEL

Write Enable Latch Status

Device is not write enabled (default).

Device is write enabled.

RDY/BSY

Ready/Busy Status

Device is ready.

Device is busy with an internal operation.

Only bit 7 of the Status/Control register will be modified when using the Write Status Register command.

R/W = Readable and writable

R = Readable only

In Ultra-Deep Power-Down Mode, all bits, including the DPDS bit, reads as 1

Even though EPE is a volatile bit, it will not be cleared when the device enters Auto Ultra-Deep Power-Down. In this case, it is not erased by a JEDEC Hardware Reset

or by exercising the RESET pin. However, it is erased on a full power cycle.

Table 12-3. Status/Control Register Format - Byte 1

Bit (1)

Name

Type (2)

Description

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