ATXP032 datasheet(63/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

12.2.5 PS (Program Suspend Status)

The PS bit indicates if a program operation has been suspended. If the PS bit is a Logic 1, then a program

operation has been suspended. See Section 9.6 for details about Program/Erase Suspend (B0h) and what

commands are allowed when the device is in this state.

12.2.6 ES (Erase Suspend Status)

The ES bit indicates whether or not an erase operation has been suspended. If the ES bit is a Logic 1, then an

erase operation (block, sector, or chip) has been suspended. See Section 9.6 for details about Program/Erase

Suspend (B0h) and what commands are allowed when the device is in this state.

12.3

Status/Control Register Byte 3

In octal mode, the “Burst Read with Wrap (0Ch)” instruction is used to perform the read operation with the “Wrap

Around” feature.

12.3.1 Wrap Length Bits

The wrap length bits are stored in the W6 and W5 bits of Status/Control Register Byte 3. The wrap-around mode is

set by W7. The wrap length and wrap mode set in either SPI or octal mode is still valid in any other mode. The wrap

bits do not have to be set again after changing mode.

If W7 is cleared, the “Burst Read with Wrap (0Ch)” instruction operates in continuous mode. It then reads to the

end of the line, wrap around to the beginning and continue reading the same line continuously for as long as

additional clock pulses are sent to SCK.

If W7 is set, the Burst Read with Wrap (0Ch) command reads to the end of the line, wrap around to the beginning

and continue reading the same line until all bytes of the first line have been read out once. In the next clock cycle,

the device starts reading at the beginning of the next line. This speeds up the loading of multiple cache lines in

cached MCUs significantly, and can increase the system throughput by 40% or more without increasing system

clock speeds.

See Table 12-7 below for wrap length settings.

12.3.2 WPP Bit

The WPP bit can be read to determine if the WP pin has been asserted or not. If the WP pin is floating, the WPP bit

as an undefined value. This bit is only used in single SPI mode. In octal mode, this bit is undefined.

12.3.3 Dummy Clock Bits

The P3 - P0 bits are used to set the number of dummy clock cycles used for the 0Bh and 0Ch read commands.The

default value after power up is 22, as this value always works independent of frequency. A lower value may be set

for lower operating frequencies as described in Table 12-8, Dummy Clock Cycles and Maximum Operating

Frequency — -40 oC to +85 oC.

In octal mode, to accommodate a wide range of applications with different needs for either maximum read

frequency or minimum data access latency, byte 3 of the Status/Control register can be used to configure the

number of dummy clocks for the Fast Read (0Bh), Read OTP Security Register (77h) and Burst Read with Wrap

(0Ch) commands, and to configure the number of bytes of ‘wrap length’ for the Burst Read with Wrap (0Ch)

command.

The dummy clocks for other Fast Read commands in Standard SPI mode are fixed, please refer toTable 7-1 for

details.

The default “wrap length” after a power up or a Reset command is 8 bytes, continuous mode. The default number

of dummy clocks is 22. The number of dummy clocks is only programmable for Fast Read (0Bh), Read OTP

Security Register (77h) and “Burst Read with Wrap (0Ch)” command in octal mode.

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