ATXP032 datasheet(16/113 Pages) DIALOG

16 / 113 page

ATXP032

DS-ATXP032–114I–4-2020

Figure 6-4.

Single Data Rate (SDR) Operation in Octal Mode — Write Operations

6.3

Dual Data Rate Operation

The ATXP032 allows Dual Data Rate (DDR) operation in octal mode for additional increase of throughput speed.

Dual data rate operation is enabled by setting the SDR/DDR bit in Status/Control Register Byte 2.

Operation using DDR mode is identical to using Single Data Rate (SDR) mode, except that both edges of the clock

are used for clocking address and data. Commands are clocked on the rising edge of SCK, requiring a whole clock

cycle also in the DDR mode. In addition, for DDR mode 4 (or more) dummy cycles are required as shown in

Figures 6-5 and 6-6. An additional half dummy cycle is required for Octal DDR as described in Figure 6-5. The

number of dummy cycles required for each command is described in Tables 7-1 and 7-3, and in the individual

command descriptions. For read commands to the Flash memory array, the number of dummy cycles is dependent

on the clock frequency used. See Section 12.3, Status/Control Register Byte 3, for details.

Note that for DDR operation in octal mode, all read and write operations operate on an even number of bytes. The

minimum number of SCK pulses for clocking data is one, and as data is clocked on both edges, two bytes are read

or written. Address bit A

0 has to be always 0 in this mode to ensure correct alignment of the two bytes read or

written. If address bit A0 is set to 1, it is ignored and treated as A0 = 0 by the device. For register operations that

operate on a single 8-bit register, a read operation outputs the same register value on the first clock edge and the

data on the second clock edge is unpredictable. For write operations on a single 8-bit register read operation, only

the value on the first clock edge is written and the data on the second clock edge is ignored.

For high speed operation, the signal delays in the system need to be taken into account. The signal path going

from the SPI master to the memory device and back may cause so much skew between the SCK and the data that

the data read from the memory device is no longer synchronized with the outgoing SCK signal as seen by the SPI

master.

MSB

Input Data

Byte1

Byte2

A16

A17

A18

A10

A19

A11

A20

A12

A21

A13

A22

A14

A23

A15

Address Bits A

-A

A24

A25

A26

A27

A28

A29

A30

A31

MSB

Opcode

I/O0

(SI)

SCK

I/O1

(SO)

I/O2

(WP)

I/O3

I/O4

I/O5

I/O6

I/O7

ATXP032 датащи(PDF) 16 Page - Dialog Semiconductor

ATXP032 датащи(HTML) 16 Page - Dialog Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL