ATXP032 datasheet(85/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

13.7.1 JEDEC Hardware Reset

The Exit Ultra-Deep Power-Down / JEDEC Hardware Reset command sequence can be used to wake-up the

device from ultra-deep power-down. This sequence can also be used to reset the device to its power on state

without cycling power. See Section 13.9 for details on JEDEC Standard Hardware Reset (In-Band Reset). See also

Section 14.6, AC Characteristics, All Other Parameters, for timing details.

13.7.2 Hardware Reset

The hardware RESET pin can be used to wake up the device from UDPD mode. This option can also be used to

reset the device to a state similar to the power-on state without cycling power. See Section 13.10 for details on

Hardware Reset. See also Section 14.6, AC Characteristics, All Other Parameters, for timing details.

13.7.3 Power Cycling

The device can also exit the UDPD mode by power cycling the device. Note that the time t

PUW power-up device

delay before program or erase allowed applies in this case. See Section 15.1, Power-Up/Power-Down Voltage and

Timing Requirements, for details.

13.8

Terminate (F0h)

In some applications, it may be necessary to prematurely terminate a program or erase operation rather than

waiting for the program or erase operation to complete normally. The Terminate command allows a program or

erase operation in progress to be ended abruptly and returns the device to an idle state. Since the need to reset

the device is immediate, the Write Enable command does not need to be issued prior to the Terminate command.

Therefore, the Terminate command operates independently of the state of the WEL bit in the Status/Control

The Terminate command can be executed only if the command has been enabled by setting the Terminate

Enabled (TERE) bit in the Status/Control register to a logic 1 using the Write Status Register Byte 2 (31h)

command. This command should be entered before a program command is entered. If the terminate operation has

not been enabled (the TERE bit is in the logic 0 state), then any attempts at executing the Terminate command are

ignored.

To perform a terminate operation, the CS pin must first be asserted, and then the command F0h must be clocked

into the device. No address bytes need to be clocked in, but a confirmation byte of D0h must be clocked into the

device immediately after the command. Any additional data clocked into the device after the confirmation byte is

ignored. When the CS pin is deasserted, the program operation currently in progress is terminated within a time of

tSWRST. Since the program or erase operation may not complete before the device is reset, the contents of the page

being programmed or erased cannot be guaranteed to be valid.

The Terminate command has no effect on the states of the Configuration Register or TERE bit in the

Status/Control register. The WEL bit is reset back to its default state.

The complete command and confirmation byte must be clocked into the device before the CS pin is deasserted,

and the CS pin must be deasserted on a whole byte boundary (multiples of eight bits); otherwise, no reset

operation is performed.

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