ATXP032 datasheet(56/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Figure 11-3. Program OTP Security Register in Octal Mode — DDR

11.2

Read OTP Security Register (77h)

The OTP Security register can be sequentially read in a similar fashion to the read array operation up to the

maximum clock frequency specified by f

CLK. To read the OTP Security register, the CS pin must first be asserted

and the 77h command must be clocked into the device. After the command has been clocked in, the four address

bytes must be clocked in to specify the starting address location of the first byte to read within the OTP Security

After the four address bytes have been clocked in, one or more additional dummy bytes need to be clocked into the

device. For the SPI Mode, one dummy byte is used. For octal mode, 8 or more dummy cycles are used as shown

in Table 12-8, Dummy Clock Cycles and Maximum Operating Frequency — -40

oC to +85 oC. Note that the table

refers to full clock cycles, also for DDR modes. Half cycles are not used for dummy cycles, the settings are a

multiple of 2 full cycles.

After the four address bytes and the dummy cycles have been clocked in, additional clock cycles result in data

being output on the I/O pin(s). The data is always output with the MSB of a byte first. When the last byte (0000FFh)

of the OTP Security register has been read, the device continues reading back at the beginning of the register

(000000h). No delays are incurred when wrapping around from the end of the register to the beginning of the

Deasserting the CS pin terminates the read operation and put the I/O pin(s) used into a high-impedance state. The

CS pin can be deasserted at any time and does not require that a full byte of data be read.

Figure 11-4. Read OTP Security Register

Data In

Byte1 Byte2

Address

Bits A

-A

9Bh

Opcode

I/O7-0

SCK

MSB

LSB

MSB

Output Data Byte 1

Dummy Byte

Address Bits A31-A0

Opcode

10 11

48 49

52 53

37 38

41 42

45 46

SCK

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