ATXP032 datasheet(10/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

WP (I/O

WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please

refer to

“Protection Commands and Features” on page 42 for more details on protection

features and the WP pin.

In octal mode, the I/O

2 pin is used together with I/O7-0 as a bidirectional I/O pin. In these

modes, the I/O2 pin is placed in the high-impedance state whenever the device is deselected

(CS is deasserted).

The WP pin is internally set to a logic 1 state at power up.

The WP pin is used for write protection control in standard SPI mode (1-1-1). The WPP bit in

Status/Control register byte 3 reflects the current state of WP pin.

If the ATXP032 is installed in a system which supports only standard SPI mode, and write

protection control is not needed, the WP pin can be left floating. In this case the value of the

WPP bit is undefined.

Once the WP pin is used in standard SPI mode, it should be always driven.

If the ATXP032 is installed in a system which also supports octal mode, the WP pin functions

as write protection control only in standard SPI mode. In this case, if write protection control is

required, the WP pin must be driven externally when the device is switched from OPI to

standard SPI mode.

In octal mode the WPP bit value is undefined and write protection control logic behaves as if

the WP pin is connected to a logic 1 state.

Low

Input/

Output

I/O

3 : In octal mode, I/O3 is used together with I/O7-0 as a bidirectional I/O pin. In these modes,

the I/O

3 pin is placed in the high-impedance state whenever the device is deselected (CS is

deasserted).

The I/O3 pin should be kept in high-Z state or pulled high while in SPI mode.

Input/

Output

DATA STROBE: DS is the return of the SCK clock, synchronized to the return data. It is

available in all modes, and makes it easier to achieve high clock speeds in a system. DS is

required to achieve maximum clock speeds.

DS is driven low as soon as CS is driven low by the host controller, and is driven until CS is

pulled high again. DS is only toggled while the device is transmitting data. DS remains low

while the device is receiving commands, address and data.

In Single Data Rate (SDR) mode, DS is driven high in the first half of the data output cycle, and

low in the second half. In this mode, DS is basically the inverse of SCK, but with a delay. If

SCK is low at the end of an operation, DS will be high. This is the recommended mode of

operation in SDR mode. However, if the host controller requires DS to end low to be able to

use this signal correctly, it is also possible to add half of an SCK pulse and end with SCK high

and DS low.

In DDR mode, DS changes value at the edge of each data bit. In this mode, DS is basically the

same value as SCK, but with a delay.

Achieving high clock rates in systems without DS requires a short signal path between the SPI

master and the memory device, and careful layout of all signal lines to minimize signal delays.

Output

I/O

7, I/O6,

I/O5, I/O4

SERIAL I/O: In octal mode, I/O7-4 are used together with I/O3-0 as bidirectional I/O pins. In this

mode, the I/O

7-4 pins (as well as the I/O3-0 pins) are placed in the high-impedance state

whenever the device is deselected (CS is deasserted).

In standard SPI mode, the I/O

7-4 pins are always in a high-impedance state.

Input/

Output

Table 4-1.

Pin Descriptions (Continued)

Symbol

Description

Asserted

State

Type

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