ATXP032 datasheet(92/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

13.15 Return to Standard SPI Mode (FFh)

In order to exit the octal mode and return to the standard SPI mode, a Return to Standard SPI Mode command

must be issued.

Before the Return to Standard SPI Mode command can be issued, the Write Enable (06h) command must have

been previously issued to set the WEL bit in the Status/Control register to a logic 1.

To issue the Return to Standard SPI Mode command, the CS pin must first be asserted and the command of FFh

must be clocked into the device.

The WEL bit in Status/Control register byte 1 is reset back to the logic ‘0’ state. The SDR/DDR and OME bits in

Status/Control register byte 2 are all set to 0. The device returns to standard SPI mode, SDR, independent of

which mode it was in prior to issuing this command.

Figure 13-22. Return to Standard SPI Mode from Octal Mode — SDR

Figure 13-23. Return to Standard SPI Mode from Octal Mode — DDR

13.16 Read SFDP (5Ah)

The ATXP032 contains a 256-byte Serial Flash Discoverable Parameter (SFDP) register.

The SFDP register can be sequentially read in a similar fashion to the read array operation up to the maximum

clock frequency specified by f

RDLF. To read the SFDP security register, the CS pin must first be asserted and the

command of 5Ah must be clocked into the device. After the command has been clocked in, the three address bytes

must be clocked in to specify the starting address location of the first byte to read within the SFDP security register.

Following the three address bytes, eight additional dummy cycles (8 dummy cycles = 1 dummy byte in SPI mode)

need to be clocked into the device. Note that this means eight complete clock cycles, also for DDR modes. Octal

DDR mode has an additional 1/2 dummy cycle, due to clock alignment.

Note that even though this device otherwise is using 4-byte addressing, SFDP is always using 3-byte addressing.

FFh

Opcode

I/O7-0

SCK

FFh

Opcode

I/O7-0

SCK

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