ATXP032 datasheet(18/113 Pages) DIALOG

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ATXP032

DS-ATXP032–114I–4-2020

Figure 6-6.

Dual Data Rate (DDR) Operation in Octal Mode — Write Operations

Commands and Addressing

A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been

asserted, the host controller must then clock out a valid 8-bit command on the SPI bus. Following the command,

instruction-dependent information such as address and data bytes would then be clocked out by the host

controller. All command, address, and data bytes are transferred with the most-significant bit (MSB) first. An

operation is ended by deasserting the CS pin.

Device behavior is not defined for commands not supported by the ATXP032. Commands not described in this

document should therefore be avoided.

If the CS pin is deasserted before complete command and address information is sent to the device, then no

operation will be performed and the device simply returns to the idle state and waits for the next operation.

Addressing of the device requires a total of four bytes of information to be sent, representing address bits A

31 - A0.

Since the upper address limit of the ATXP032 memory array is 3FFFFFh, address bits A

31 - A22 must be zero for

proper operation.

MSB

Input

Data

Byte1 Byte2

A16 A8 A0

A17 A9 A1

A18 A10 A2

A19 A11 A3

A20 A12 A4

A21 A13 A5

A22 A14 A6

A23 A15 A7

A24

A25

A26

A27

A28

A29

A30

A31

Address

Bits A

-A

MSB

Opcode

I/O0

(SI)

SCK

I/O1

(SO)

I/O2

(WP)

I/O3

I/O4

I/O5

I/O6

I/O7

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