ADRF6821 datasheet(26/61 Pages) AD

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ADRF6821

Data Sheet

Rev. A | Page 26 of 61

Pin No.

Mnemonic

Description

Basic Connection

3.3 V RF/IF Power

15, 56

VCC_3V3_I, VCC_3V3_Q

Supply for DSA and RF

switches

Decouple these power supply pins to ground

using 100 pF, 0.1 µF, and 10 µF capacitors. Place

the decoupling capacitors close to these pins.

6, 8

VCC_LO1, VCC_LO2

LO path to mixer supply

Decouple these power supply pins to ground

using 100 pF and 0.1 µF capacitors. Place the

decoupling capacitors close to these pins.

22, 49

VCC_IFMIX_I,

VCC_IFMIX_Q

Mixer supply

20, 51

VCC_IFMIX_I,

VCC_IFMIX_Q

IF amplifier supply

VCM Input

1, 14

VCM_Q, VCM_I

VCM adjust pins

Decouple the VCM input pins to ground using

100 pF and 0.1 µF capacitors and connect these

pins to the same supply domain as the

VCC_IFMIX_Q and VCC_IFMIX_I pins. Place the

decoupling capacitors close to the pins. Place a

resistive divider to divide the supply voltage into

two. Use 5.1 kΩ (or similar) for resistive divider

component values.

Decoupling

VDD_DIG

Decoupling pin for the

internal LDO to supply the

internal digital circuits

Decouple these pins to ground using 100 pF and

0.1 µF capacitors. Place the decoupling capacitors

close to these pins.

21, 50

VDCPL_I, VDCPL_Q

Decoupling pins for I and Q

channels

IF Outputs

17, 18, 53, 54

IF_IOUT+, IF_IOUT−,

IF_QOUT−, IF_QOUT+

I and Q outputs

Place 25 Ω resistors in series for each differential

leg. The differential I/Q output impedance

together with the series 25 Ω resistors becomes

60 Ω. For optimized performance, the 60 Ω output

impedance must be terminated with a 100 Ω load.

3.3 V PLL/VCO Power

VCCVCO_3V3

VCO 3.3 V supply

Decouple these power supply pins to ground using

100 pF and 0.1 µF capacitors. Place the decoupling

capacitors close to the pins. Employ ferrite beads

to provide isolation between the PLL/VCO supply

pins. Beware of the series resistance of the ferrite

beads and try to minimize the voltage drop.

VCCDIV_3V3

LO chain and divider 3.3 V

supply

VCCFBDIV_3V3

PLL feedback divider 3.3 V

supply

VCCLO_MIX_3V3

LO mixer output buffer 3.3 V

supply

VCCLO_AUX_3V3

LO external output buffer

3.3 V supply

VCCCP_3V3

Charge pump 3.3 V supply

VCCPFD_3V3

PFD 3.3 V supply

VCCREF_3V3

Reference input buffer 3.3 V

supply

VBAT_DIG_3V3

SPI and SDM LDO 3.3 V

supply

PLL/VCO

LO_LCKDT

LO lock detect

DCL_BIAS

VCO core bias decouple

Decouple this pin to ground using a 0.1 µF capacitor.

VTUNE

VTUNE input

This pin is driven by the output of the loop filter;

its nominal input voltage range is 1.5 V to 2.5 V.

CPOUT

Charge pump output

Connect this pin to the VTUNE pin through the

loop filter.

REF_IN

Reference input buffer

The nominal input level of this pin is 1 V p-p. The

input range is 10 MHz to 250 MHz. This pin is

internally biased and must be ac-coupled and

terminated externally with a 50 Ω resistor. Place

the ac coupling capacitor between the pin and

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