ADRF6821 datasheet(24/61 Pages) AD

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ADRF6821

Data Sheet

Rev. A | Page 24 of 61

Quadrature Divider

The quadrature divider block divides the 2× LO frequency

generated by either the internal PLL and VCO or the external

input by 2. Next, the quadrature divide block generates two

LO signals with a 90° phase difference. To enable the divider,

disable the bits, EN_IBIASGEN (Register 0x0090, Bit 0),

EN_DIVPATH_BUF (Register 0x0090, Bit 1), and

EN_DIVPATH_QUADDIV (Register 0x0090, Bit 2). Two

separate LO drivers take these LO signals and feed them to the

mixers. LO driver paths are enabled via the following registers:

•

EN_LODRV_DRVI (Register 0x0090, Bit 3)

•

EN_LODRV_DRVQ (Register 0x0090, Bit 4)

•

EN_LODRV_PREDRVI (Register 0x0090, Bit 5)

•

EN_LODRV_PREDRVQ (Register 0x0090, Bit 6)

The proper register write sequence starts with locking the LO

frequency or enabling the external LO inputs. After ensuring that

the local oscillator is locked in either the internal PLL/VCO or

the external LO source, enable the LO_OE bit (Register 0x1414,

Bit 6). After enabling the LO_OE bit, the RF and IF blocks can

be enabled as defined in the Theory of Operation section.

SERIAL PERIPHERAL INTERFACE (SPI)

The SPI of the ADRF6821 allows the user to configure the

device for specific functions or operations through a structured

users with added flexibility and customization. Addresses are

accessed via the SPI and can be written to or read from the SPI.

The serial peripheral interface consists of four control lines:

SCLK, SDIO, SDO, and CS. The serial clock (SCLK) is the serial

shift clock, and it synchronizes the serial interface reads and

writes. SDIO is the serial data input or the serial data output

depending on the instruction sent and the relative position in

the timing frame. Chip select bar (CS) is an active low control

that gates the read and write cycles. The falling edge of CS in

conjunction with the rising edge of SCLK determines the start

of the frame. When CS is high, all SCLK and SDIO activity is

ignored. See Table 6 for the serial timing and its definitions.

The ADRF6821 protocol consists of a read/write followed by

16 register address bits and 8 data bits. Both the address and

data fields are organized with the most significant bit (MSB)

first and end with the least significant bit (LSB).

The SPI and general-purpose input/output (GPIO) interfaces of

the ADRF6821 provides two options for the logic voltage levels,

1.8 V and 3.3 V. The interfaces use 1.8 V logic levels as the

default. Enable SPI_18_33_SEL (Register 0x0020, Bit 0) and

SPI_1P8_3P3_CTRL (Register 0x1401, Bit 4) for 3.3 V compatible

logic levels. See Table 6 for the SPI specifications.

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