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ADRF6821 датащи(PDF) 25 Page - Analog Devices

номер детали ADRF6821
подробное описание детали  450 MHz to 2800 MHz, DPD RFIC with Integrated Fractional-N PLL and VCO
PDF  61 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADRF6821 датащи(HTML) 25 Page - Analog Devices

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Data Sheet
ADRF6821
Rev. A | Page 25 of 61
APPLICATIONS INFORMATION
BASIC CONNECTIONS
RFIN_FB1
100pF
RF INPUT 0
17
18
24 25 26 27
DC DAC
÷2
SPI
/N
PFD
Δ-Σ
/R
0
90
11
10
9
4
54
53
45
41
32
30
31
DC DAC
RFIN_FB0
100pF
RF INPUT 0
CPOUT
VTUNE
EX_LO_IN–
EX_LO_IN+
100pF
100pF
RF_SEL0
RF_SEL1
CP
25Ω
35.7Ω
39Ω
220Ω
220Ω
VTUNE
CPOUT
0.1µF
I OUTPUT
TC 1-1-13MX+
25Ω
35.7Ω
0.1µF
39Ω
4300pF
4300pF
0.12µF
EX LO INPUT
TCM 1-8 3X+
25Ω
35.7Ω
39Ω
0.1µF
Q OUTPUT
TC 1-1-13MX+
25Ω
35.7Ω
0.1µF
39Ω
÷
Figure 47. Typical Application Circuit
Table 15. Typical Connections
Pin No.
Mnemonic
Description
Basic Connection
RF Inputs
4, 11
RFIN_FB0, RFIN_FB1
RF inputs
The single-ended RF inputs have a 50 Ω impedance.
These pins must be ac-coupled. Terminate unused
RF inputs with a dc blocking capacitor to ground
to improve isolation. Refer to the Layout section
for the recommended PCB layout.
RF Balun Optimization
7
RFBT_FB
RF balun tuning inductor
Connect the balun tuning inductor (LTUNE) to ground.
GPIOs
9, 10
RF_SEL0, RF_SEL1
RF select control pins
Active high. 1.8 V and 3.3 V logic level compatible.
See the Theory of Operation section for RF select
pin use.
13
SLEEP
Sleep mode enable pin
Active high. 1.8 V and 3.3 V logic level compatible.



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