ADRF6821 datasheet(6/61 Pages) AD

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ADRF6821

Data Sheet

Rev. A | Page 6 of 61

PLL/VCO SPECIFICATIONS

All supply pins = 3.3 V, TA = 25°C, reference frequency (fREF) = 122.88 MHz, fREF power = 10 dBm, PFD frequency (fPFD) = 30.72 MHz, and

loop filter BW = 20 kHz, unless otherwise noted.

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

PLL REFERENCE

Frequency

30.72

250

MHz

Level

For PLL lock condition, 50 Ω to ground required

close to REF_IN pin

0.7

3.3

V p-p

Step Size

240

kHz

Lock Time

For PLL lock condition

0.4

PFD FREQUENCY, fPFD

30.72

61.44

MHz

INTERNAL VCO RANGE

4000

8000

MHz

OPEN-LOOP VCO PHASE NOISE

VCO Frequency (fVCO) = 5440 MHz

10 kHz offset

−83

dBc/Hz

100 kHz offset

−110

dBc/Hz

1 MHz offset

−132

dBc/Hz

10 MHz offset

−152

dBc/Hz

fVCO = 7060 MHz

10 kHz offset

−80

dBc/Hz

100 kHz offset

−106

dBc/Hz

1 MHz offset

−127

dBc/Hz

10 MHz offset

−147

dBc/Hz

SYNTHESIZER SPECIFICATIONS

Fractional Figure of Merit (FOM)

−227

dBc/Hz

Flicker FOM

−262

dBc/Hz

fPFD Spurs1

Output to internal mixer and daisy-chain of

another ADRF6821

fPFD × 1

−90

dBc

fPFD × 2

−95

dBc

fPFD × 3 and Higher

−95

dBc

Unwanted Spurs (Other Than PFD and Harmonics)1

Output to internal mixer and daisy-chain of

another ADRF6821

−70

dBc

fLO = 1765 MHz, fVCO = 7060 MHz

Closed-Loop Phase Noise

1 kHz offset

−102

dBc/Hz

10 kHz offset

−97

dBc/Hz

100 kHz offset

−117

dBc/Hz

950 kHz offset

−138

dBc/Hz

2.1 MHz offset

−145

dBc/Hz

3.5 MHz offset

−149

dBc/Hz

7.5 MHz offset

−153

dBc/Hz

10 MHz offset

−156

dBc/Hz

85 MHz offset

−158

dBc/Hz

Integrated Phase Noise

100 Hz to 10 MHz integration BW

0.2

°rms

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