ADRF6821 datasheet(23/61 Pages) AD

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Data Sheet

ADRF6821

Rev. A | Page 23 of 61

Equation 3 results in a very fine frequency resolution with no

residual frequency error. To apply this formula, take the

following steps:

1. Calculate N by VCOOUT/fPFD.

2. The integer value of this number forms INT.

3. Subtract the INT value from the full N value.

4. Multiply the remainder by 224.

5. The integer value of this number forms FRAC1.

6. Calculate MOD based on the channel spacing (fCHSP) by

MOD = fPFD/GCD(fPFD, fCHSP)

(4)

where:

GCD(fPFD, fCHSP) is the greatest common divider of the PFD

frequency and the desired channel spacing frequency.

7. Calculate FRAC2 by the following equation:

FRAC2 = ((N − INT) × 224 − FRAC1)) × MOD

(5)

The FRAC2 and MOD fraction result in outputs with zero

frequency error for channel spacings when

fPFD/GCD(fPFD/fCHSP) < 16,383

(6)

where:

fPFD is the frequency of the phase frequency detector.

GCD is a greatest common denominator function.

fCHSP is the desired channel spacing frequency.

After determining the necessary register values for PLL, set the

SD_EN_FRAC0 bit (Register 0x122A, Bit 5) to 1. In the integer

mode (when FRAC = 0), set the SD_EN_OUT_OFF bit

(Register 0x122A, Bit 4) to 1. In the same manner, set the

SD_EN_OUT_OFF bit to 0 for fractional mode (that is, when

FRAC ≠ 0).

It is recommended to set the charge pump current to be 2.4 mA,

by setting the CP_CURRENT bit (Register 0x122E, Bits[3:0]) to

8. With a 20 kHz loop filter, the charge pump current setting

results in an optimized performance.

Bleed Setting

The PFD circuitry compares the PFD and divided down VCO

signals. The ADRF6821 employs a bleed circuit to put the PFD

circuit in the linear operation region. The bleed circuit introduces a

delay to the incoming PFD signal, indicated as PFD_OFFSET in

Equation 7. Calculate the bleed current, BICP, (Register 0x122F,

Bits[7:0]), from the desired PFD_OFFSET, as shown in

Equation 7.

BICP = Integer(round(float(ICP × PFD_OFFSET ×

fPFD)/960)/255))

(7)

where:

ICP is the charge pump current.

The recommended PFD_OFFSET for the 20 kHz loop filter is 2 ns.

PLL Lock Time

The time it takes to lock the PLL after the last register is written

into two parts: VCO band calibration and loop settling.

After writing to the last register, the PLL automatically performs

a VCO band calibration to choose the correct VCO band. This

calibration requires approximately 200 µs. After calibration

completes, the feedback action of the PLL causes the VCO to

eventually lock to the correct frequency. The speed with which

this lock occurs depends on the small signal settling of the loop.

Settling time, after calibration, depends on the PLL loop filter

bandwidth. With a 20 kHz loop filter bandwidth, settling time is

approximately 200 µs.

Lock Detect Control

The ADRF6821 provides two ways of observing lock detection.

Lock detection can be monitored from a dedicated register,

LOCK_DETECT (Register 0x124D, Bit 0). Lock detection can

also be monitored through the dedicated LO_LCKDT pin (Pin 23).

Required PLL/VCO Settings and Register Write Sequence

Configure the PLL registers as described in the PLL Frequency

Programming section to achieve the desired frequency, and

the last write must be to Register 0x1200 (INT_L). When

initiates, which is the last step to locking the PLL.

External LO Mode

The external LO frequency range is 900 MHz to 5600 MHz and

2× LO signal is used with the internal quadrature divider. To

configure for external LO mode, write the following register

sequence and apply the differential LO signals to Pin 31

(EXT_LO_IN+) and Pin 32 (EXT_LO_IN−).

Table 14. Register Settings for External LO Mode

Required Value

Description

0x120B

0x00

Disable feedback divider

0x122D

0x00

Disable PFD and charge pump (CP)

0x1240

0x03

Disable VCO adjust

0x1217

0x00

Set VCO select to a low value

0x121F

0x40

Disable calibration

0x1021

0xD8

Disable PLL blocks

0x1414

0xA1

Use external LO

The EXT_LO_IN+ and EXT_LO_IN− input pins must be

ac-coupled. When not in use, leave the EXT_LO_IN+ and

EXT_LO_IN− pins unconnected.

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