ADRF6821 datasheet(20/61 Pages) AD

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ADRF6821

Data Sheet

Rev. A | Page 20 of 61

THEORY OF OPERATION

The ADRF6821 integrates many of the essential building blocks

for a high bandwidth quadrature demodulator and receiver,

especially for the feedback downconverter path for the digital

predistortion in cellular base stations. The main features include

two single-pole, double-throw (SPDT) RF input switches, a

balun, a variable RF attenuator, a pair of active mixers, and two

baseband buffers. Additionally, the local oscillator (LO) signals

for the mixers are generated by a fractional-N synthesizer and a

multicore voltage controlled oscillator (VCO), covering an octave

frequency range with low phase noise. A pair of flip-flops then

divides the LO frequency by two and generates the in phase and

quadrature phase LO signals to drive the mixers. The synthesizer

uses a fractional-N phase-locked loop (PLL) with additional

frequency dividers to enable continuous LO coverage from

450 MHz to 2800 MHz.

The signal path through the device begins at one of two RF

inputs, RFIN_FB0 and RFIN_FB1, selected by the RF switches.

The selected single-ended input converts to a differential signal

via the integrated balun. The differential RF signal attenuates to

an optimal input level via the digital step attenuator with 15 dB

of attenuation range in 1 dB steps. The RF signal then mixes

with the LO signal in the Gilbert cell mixers down to an

intermediate frequency (IF) or baseband. From the mixer, the

signal passes through a wideband low-pass filter to remove the

higher order mixing terms, followed by a fixed gain linear IF

amplifier.

The different sections of the ADRF6821 are controlled through

registers programmable via a serial peripheral interface (SPI).

The EN_ANALOG_MASTER bit (Register 0x0020, Bit 1) is the

master enable for all enables related to the RF switch, attenuator,

mixer, IF amplifiers, divider, and LO drivers. This bit does not

control any of the enables related to LO generation blocks.

RF INPUT SWITCH

The ADRF6821 incorporates two SPDT switches, which allow

one RF input to be selected while the other RF input can be

correctly terminated to 50 Ω. Selection of the desired RF input

is achieved externally via two control pins or serially via register

writes to the SPI. When compared to the serial write approach,

pin control allows faster switching between the RF inputs. Using

the RF_SEL0 and RF_SEL1 pins (Pin 9 and Pin 10, respectively),

the RF input can be switched from one channel to the other

quickly and settle the IF output within 2 µs. When the input is

controlled via the SPI serial port, the time for the serial data

transfer must also be considered and is dependent on the serial

interface clock rate.

The SEL_RFSW_SPI_CONTROL bit (Register 0x0030, Bit 6)

selects whether the RF input switch is controlled via the external

pins or via the SPI (see Table 10). By default at power-up, the

device is configured for pin control. In serial mode control,

writing to the RFSW_SEL0 bit (Register 0x0030, Bit 4) allows

selection of RF Input 0 and writing to the RFSW_SEL1 bit

(Register 0x0030, Bit 5) allows selection of RF Input 1. If only

one RFINx port is used, the unused RF input must be properly

terminated to improve isolation. It is recommended to use a dc

blocking capacitor to GND as termination. Figure 45 shows the

recommended configuration when only RFIN_FB0 is employed.

RFIN_FB0

ADRF6821

50Ω

100pF

RFIN_FB1

Figure 45. Terminating the Unused Port of the ADRF6821

Table 10. RF Input Selection1

SEL_RFSW_SPI_CONTROL Bit,

(Register 0x0030, Bit 6)

RFSW_SEL0 Bit,

(Register 0x0030, Bit 4)

RFSW_SEL1 Bit,

(Register 0x0030, Bit 5)

RF_SEL0 and RF_SEL1 Pins

RF Input Pin

RF_SEL0

RFIN_FB0

RF_SEL1

RFIN_FB1

RFIN_FB0

RFIN_FB1

X means don’t care.

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