ADRF6821 datasheet(21/61 Pages) AD

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Data Sheet

ADRF6821

Rev. A | Page 21 of 61

BALUN

The ADRF6821 integrates a balun operating over a 450 MHz to

2800 MHz frequency range. The wideband balun offers the

benefit of ease of drivability with single-ended, 50 Ω RF inputs,

and the single-ended to differential conversion of the integrated

balun provides additional common-mode noise rejection.

RF ATTENUATOR

The RF digital step attenuator follows the balun, and the

attenuation range is 0 dB to 15 dB with a step size of 1 dB.

The ATTEN_DSA bits (Register 0x0031, Bits[5:2]) in the

DSA_CONTROL register determine the setting of the RF

digital step attenuator. The EN_DSA (Register 0x0031, Bit [0])

bit enables the RF attenuator.

ACTIVE MIXER

After the RF digital step attenuator, the RF signal is split and

provided to a pair of double balanced, Gilbert cell active mixers.

The RF signal is then downconverted by the on-chip LO at the

mixer, resulting in a baseband output. Enable the mixer and the

common-mode controls as listed in Table 11.

Table 11. Demodulator Enable Registers

Value

Description

0x0032

0x3E

Demodulator enables

0x0040

0x0F

Common-mode control enables

0x0033

0x2D

Mixer LO common-mode control

0x0034

0x2D

Mixer output stage common-

mode control

The ADRF6821 provides a gain peaking circuit to increase the

gain for high RF. The amount of gain peaking is controlled by

the MIXER_GAIN_PEAK bits (Register 0x003A, Bits[1:0]).

Note that increased gain leads to slight degradation of the

linearity performance.

The ADRF6821 uses dc compensation digital-to-analog converters

(DACs) for both I and Q outputs. DC compensation covers a

range of ±40 mV. Control the dc compensation value via the

CODE_DC_IDAC_RF0 bits (Register 0x0051) for the I output

and the CODE_DC_QDAC_RF0 bits (Register 0x0052) via the

Q output for Channel 0. For Channel 1, use the CODE_DC_

IDAC_RF1 bits (Register 0x0053) for the I output and the

CODE_DC_QDAC_RF1 bits (Register 0x0054) for the Q output.

The control words are in signed magnitude format and eight bits

wide. The effective least significant bit (LSB) is approximately

0.5 mV.

I AND Q POLARITY

The ADRF6821 offers the flexibility of specifying the polarity of

the I and Q outputs, where I can lead Q or vice versa. By addressing

SEL_LODRV_PREDRVI_POL (Register 0x0080, Bit 1) or

SEL_LODRV_PREDRVQ_POL (Register 0x0080, Bit 2), both

the I and Q outputs can be inverted from their default configuration.

The flexibility of specifying the polarity becomes important

when the I and Q outputs are processed simultaneously in the

complex domain, I + jQ.

At power-up, depending on the whether high-side or low-side

injection of the LO frequency is applied, the I channel can

either lead or lag the Q channel by 90°. When the RF frequency

is greater than the LO frequency (low-side LO injection), the

Q channel leads the I channel. On the contrary, if the RF

frequency is less than the LO frequency (high-side LO

injection), the I channel leads the Q channel by 90°.

LOW-PASS FILTERS (LPF) AND IF AMPLIFIERS

From the mixer, the IF or baseband outputs pass through an

integrated adjustable LPF to remove the unwanted mixing

product. The LPF bandwidth is adjustable over four steps, as

listed in Table 12.

Table 12. LPF Bandwidth Selection

EN_LPF_LB_I

(Register 0x0060, Bit 0)

EN_LPF_LB_Q

(Register 0x0060, Bit 1)

LPF

Bandwidth

1 GHz

750 MHz

500 MHz

250 MHz

From the LPF, the IF or baseband signal passes to a linear

output amplifier to drive the baseband output pins (IF_IOUT+,

IF_IOUT−, IF_QOUT−, and IF_QOUT+). The IF amplifier

provides the overall gain for the ADRF6821 and, with the

required 25 Ω series resistors, allows the ADRF6821 to drive

a 100 Ω load directly. The ADRF6821 can be interfaced to a

variety of analog-to-digital converters (ADCs), and the

common-mode output can be adjusted with the external VCM

pin. The IF amplifiers are enabled through the EN_IFAMP_I

bit (Register 0x0070, Bit 0) and the EN_IFAMP_Q bit

(Register 0x0070, Bit 1).

LO GENERATION BLOCK

The ADRF6821 supports the use of both internal and external

LO signals for the mixers. The internally generated or externally

supplied 2× LO signal is fed to the quadrature divider. The

quadrature divider block divides the 2× LO frequency by 2 and

then generates two LO signals with a 90° phase difference.

The internal 2× LO is generated by an on-chip VCO, which is

tunable over a frequency range of 4000 MHz to 8000 MHz. The

output of the VCO is phase locked to an external reference clock

through a fractional-N PLL that is programmable through the SPI

control registers. To produce 2× LO signals over the 900 MHz to

5600 MHz frequency range to drive the LO divider, steer the

VCO outputs through an output divider. Alternatively, an

external signal can be used with the dividers to generate the

2× LO signals to the quadrature divider and the demodulators.

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