ADRF6821 datasheet(34/61 Pages) AD

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ADRF6821

Data Sheet

Rev. A | Page 34 of 61

LAYOUT

Careful layout of the ADRF6821 is necessary for optimizing

performance and minimizing stray parasitics. Because the

ADRF6821 supports two channels, the layout of the RF section

is critical in achieving isolation between channels. Figure 64

shows the recommended layout for the RF inputs. The best

layout approach is to keep the traces short and direct. In

addition, for improved isolation, do not route the RF input

traces in parallel to each other and spread the traces immediately

after each one leaves the pins. Keep the traces as far away from

each other as possible (and at an angle, if possible) to prevent

cross coupling.

The input impedance of the RF inputs is 50 Ω, and the traces

leading to the pin must have a 50 Ω characteristic impedance.

Terminate the unused RF inputs with a dc blocking capacitor to

ground.

Figure 64. RF/IF Domain Layout

The ADRF6821 incorporates a very low noise PLL/VCO and

care must be taken when designing the PCB routing around the

PLL/VCO pins. It is required to put the decoupling capacitors

for the supply pins as close as possible. If 0402 capacitors are

used, putting all of the decoupling capacitors close to the pin

becomes problematic. In such a case, place the smaller value

decoupling capacitor as close as possible to the pin. It is a good

practice to keep the first capacitor of the loop filter close to the

CPOUT pin, and the last capacitor close to the VTUNE pin, as

can be seen in Figure 65.

Figure 65. PLL/VCO Domain Layout

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