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ADRF6821 датащи(PDF) 60 Page - Analog Devices

номер детали ADRF6821
подробное описание детали  450 MHz to 2800 MHz, DPD RFIC with Integrated Fractional-N PLL and VCO
PDF  61 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADRF6821 датащи(HTML) 60 Page - Analog Devices

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ADRF6821
Data Sheet
Rev. A | Page 60 of 61
Address: 0x154C, Reset: 0x00, Name: RDIV2_SEL_SLAVE
Reference Divide by 2
1: Reference Divide by 2 Enabled.
0: Reference Divide by 2 Disabled.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:1] RESERVED
[0] RDIV2_SEL_SLV (R)
Table 92. Bit Descriptions for RDIV2_SEL_SLAVE
Bits
Bit Name
Settings
Description
Reset
Access
[7:1]
RESERVED
Reserved.
0x0
R
0
RDIV2_SEL_SLV
Reference Divide by 2
0x0
R
0
Reference Divide by 2 Disabled
1
Reference Divide by 2 Enabled
Address: 0x1583, Reset: 0x00, Name: DISABLE_CFG
Disable the Phase Adjust from the SPI
Register
De lay the DSM Clo ck Launch.
If Double Buffering Is Disabled, a R_DIV
Write Resets Rdivider
Disable the Generation of Frequency
Hop from the SPI Register
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[ 7 :5 ] RES ERV ED
[ 0 ] D IS ABLE_P H AS EAD J ( R/W )
[ 4 :3 ] D S M _LAUN CH _D LY ( R/W )
[ 1 ] D IS ABLE_D BLBUFFERIN G ( R/W )
[ 2 ] D IS ABLE_FREQ H O P ( R/W )
Table 93. Bit Descriptions for DISABLE_CFG
Bits
Bit Name
Settings
Description
Reset
Access
[7:5]
RESERVED
Reserved.
0x0
R
[4:3]
DSM_LAUNCH_DLY
Delay the DSM Clock Launch.
0x0
R/W
2
DISABLE_FREQHOP
Disable the Generation of the Frequency Hop from the SPI Register.
0x0
R/W
1
DISABLE_DBLBUFFERING
If Double Buffering Is Disabled, a R_DIV Write Resets RDIVIDER.
0x0
R/W
0
DISABLE_PHASEADJ
Disable the Phase Adjust from the SPI Register.
0x0
R/W



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