ADRF6821 datasheet(22/61 Pages) AD

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ADRF6821

Data Sheet

Rev. A | Page 22 of 61

Internal LO Mode

For internal LO mode, the ADRF6821 uses the on-chip PLL and

VCO to synthesize the frequency of the LO signal. The PLL,

shown in Figure 46, consists of a reference path, phase and

frequency detector (PFD), charge pump, and a programmable

integer divider with prescaler. The reference path takes in a

reference clock and it is divided down by a value calculated with

a reference (R) divider together with a doubler bit and a

prescaler bit. Then the divided down reference signal passes to

the PFD. The PFD compares this signal to the divided down

signal from the VCO. The PFD sends an up or down signal to

the charge pump if the VCO signal is slow or fast compared to the

reference frequency. The charge pump sends a current pulse to

the off-chip loop filter to increase or decrease the tuning voltage

(VTUNE).

The ADRF6821 integrates multiple VCO cores covering an

octave range of 4 GHz to 8 GHz. The suitable VCO is selected

with the autotune functionality built into the chip. After the

user determines the necessary register values, a write to the

INT_L register (Address 0x1200) initiates the autotune process.

LO Frequency and Dividers

The signal coming from the VCO or the external LO inputs

passes through a series of dividers before it is buffered to drive

the demodulator. The programmable, divide by 2 stages divide

the frequency of the incoming signal by 1, 2, 4, and 8 before

reaching the quadrature divider that further divides the signal

frequency by 2 to generate the in phase and quadrature phase

LO signals for the mixers. The LO control bits (OUT_DIVRATIO,

frequency ranges are listed in Table 13.

Table 13. Output Divide Ratio for Frequency Ranges

2× LO Frequency

(MHz)

OUT_DIVRATIO

(Register 0x1414, Bits[4:0])

VCO

Frequency

900 to 1000

01000

(2× LO) × 8

1000 to 2000

00100

(2× LO) × 4

2000 to 4000

00010

(2× LO) × 2

4000 to 5600

00001

(2× LO) × 1

PLL Frequency Programming

The INT, FRAC1, FRAC2, and MOD values, in conjunction

with the R counter, make it possible to generate output frequencies

that are spaced by fractions of the PFD frequency (fPFD).

Calculate the VCO frequency (VCOOUT) by

VCOOUT = fPFD × N

(1)

where:

VCOOUT is the output frequency of the VCO (without using

the output divider).

fPFD is the frequency of the phase frequency detector. Calculate

fPFD by

fPFD = REFIN × ((1 + D)/(R × (1 + T)))

(2)

where:

REFIN is the reference input frequency.

D is the REFIN doubler bit (Register 0x120E, Bit 3).

R is the preset divide ratio of the binary 7-bit programmable

reference counter, 1 to 255, (Register 0x120C, Bits[6:0]).

T is the REFIN divide by 2 bit, set to 0 or 1, (Register 0x120E, Bit 0).

N is the desired value of the feedback counter. N compromises

216

777

MOD

FRAC2

FRAC1

INT

(3)

where:

INT is the 16-bit integer value (23 to 32,767 for the prescaler in

4/5 mode, 75 to 65,535 for the prescaler in 8/9 mode) referenced

with Register 0x1201 and Register 0x1200. The recommended

setting for the prescaler is 8/9 mode, and it is set by enabling

PRE_SEL (Register 0x120B, Bit 1).

FRAC1 is the 24-bit numerator of the primary modulus (0 to

16,777,215) referenced with Register 0x1204, Register 0x1203,

and Register 0x1202.

FRAC2 is the numerator of the 14-bit auxiliary modulus (0 to

16,383) referenced with Register 0x1234, Bits[5:0] and

MOD is the programmable, 14-bit auxiliary fractional modulus

(2 to 16,383), referenced with Register 0x1209, Bits[5:0] and

EXTERNAL

LOOP FILTER

EXT_LO_IN+

EXT_LO_IN–

CPOUT

VTUNE

N = INT +

FRAC1 +

16,777,216

FRAC2

MOD

CHARGE

PUMP

DIVIDER

PFD

PRESCALER

OUT

DIVIDER

[4:0]

TO DEMODULATOR

SEE EXTERNAL

LO MODE

SECTION

SEE PLL FREQUENCY

PROGRAMMING SECTION

SEE PLL FREQUENCY

PROGRAMMING SECTION

DIVIDE

BY 2

REF_IN

Figure 46. PLL/VCO Block Diagram

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